1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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29# Simple test script
30#
31# "m5 test.py"
32
33import m5
34from m5.objects import *
35import os, optparse, sys
36m5.AddToPath('../common')
37import Simulation
38
39parser = optparse.OptionParser()
40
41# Benchmark options
42parser.add_option("-c", "--cmd",
43 default="../../tests/test-progs/hello/bin/alpha/linux/hello",
44 help="The binary to run in syscall emulation mode.")
45parser.add_option("-o", "--options", default="",
46 help="The options to pass to the binary, use \" \" around the entire\
47 string.")
48parser.add_option("-i", "--input", default="",
49 help="A file of input to give to the binary.")
50
51execfile("Options.py")
52
53(options, args) = parser.parse_args()
54
55if args:
56 print "Error: script doesn't take any positional arguments"
57 sys.exit(1)
58
59process = LiveProcess()
60process.executable = options.cmd
61process.cmd = options.cmd + " " + options.options
62if options.input != "":
63 process.input = options.input
64
65if options.detailed:
66 #check for SMT workload

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79 smt_process.cmd = wrkld + " " + options.options
80 if inputs and inputs[smt_idx]:
81 smt_process.input = inputs[smt_idx]
82 process += [smt_process, ]
83 smt_idx += 1
84
85
86if options.timing:
87 CPUClass = TimingSimpleCPU
88 test_mem_mode = 'timing'
89elif options.detailed:
90 CPUClass = DerivO3CPU
91 test_mem_mode = 'timing'
92else:
93 CPUClass = AtomicSimpleCPU
94 test_mem_mode = 'atomic'
95
96CPUClass.clock = '2GHz'
97
98np = options.num_cpus
99
100system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
101 physmem = PhysicalMemory(range=AddrRange("512MB")),
102 membus = Bus(), mem_mode = test_mem_mode)
103
104system.physmem.port = system.membus.port
105
106for i in xrange(np):
107 if options.caches and not options.standard_switch:
108 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
109 L2Cache(size = '64kB'))
110 system.cpu[i].connectMemPorts(system.membus)
111 system.cpu[i].mem = system.physmem
112 system.cpu[i].workload = process
113
114root = Root(system = system)
115
116Simulation.run(options, root, system)