ruby_random_test.py (10300:ed3816dae6d5) ruby_random_test.py (10519:7a3ad4b09ce4)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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101 mem_ranges = [AddrRange(options.mem_size)])
102
103# Create a top-level voltage domain and clock domain
104system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
105
106system.clk_domain = SrcClockDomain(clock = options.sys_clock,
107 voltage_domain = system.voltage_domain)
108
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 92 unchanged lines hidden (view full) ---

101 mem_ranges = [AddrRange(options.mem_size)])
102
103# Create a top-level voltage domain and clock domain
104system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
105
106system.clk_domain = SrcClockDomain(clock = options.sys_clock,
107 voltage_domain = system.voltage_domain)
108
109Ruby.create_system(options, system)
109Ruby.create_system(options, False, system)
110
111# Create a seperate clock domain for Ruby
112system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
113 voltage_domain = system.voltage_domain)
114
115assert(options.num_cpus == len(system.ruby._cpu_ports))
116
117tester.num_cpus = len(system.ruby._cpu_ports)

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132 tester.cpuInstPort = ruby_port.slave
133
134 #
135 # Tell each sequencer this is the ruby tester so that it
136 # copies the subblock back to the checker
137 #
138 ruby_port.using_ruby_tester = True
139
110
111# Create a seperate clock domain for Ruby
112system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
113 voltage_domain = system.voltage_domain)
114
115assert(options.num_cpus == len(system.ruby._cpu_ports))
116
117tester.num_cpus = len(system.ruby._cpu_ports)

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132 tester.cpuInstPort = ruby_port.slave
133
134 #
135 # Tell each sequencer this is the ruby tester so that it
136 # copies the subblock back to the checker
137 #
138 ruby_port.using_ruby_tester = True
139
140 #
141 # Ruby doesn't need the backing image of memory when running with
142 # the tester.
143 #
144 ruby_port.access_phys_mem = False
145
146# -----------------------
147# run simulation
148# -----------------------
149
150root = Root( full_system = False, system = system )
151root.system.mem_mode = 'timing'
152
153# Not much point in this being higher than the L1 latency
154m5.ticks.setGlobalFrequency('1ns')
155
156# instantiate configuration
157m5.instantiate()
158
159# simulate until program terminates
160exit_event = m5.simulate(options.abs_max_tick)
161
162print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
140# -----------------------
141# run simulation
142# -----------------------
143
144root = Root( full_system = False, system = system )
145root.system.mem_mode = 'timing'
146
147# Not much point in this being higher than the L1 latency
148m5.ticks.setGlobalFrequency('1ns')
149
150# instantiate configuration
151m5.instantiate()
152
153# simulate until program terminates
154exit_event = m5.simulate(options.abs_max_tick)
155
156print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()