1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 117 unchanged lines hidden (view full) --- 126 # the tester. 127 # 128 ruby_port.access_phys_mem = False 129 130# ----------------------- 131# run simulation 132# ----------------------- 133 |
134root = Root( full_system = False, system = system ) |
135root.system.mem_mode = 'timing' 136 137# Not much point in this being higher than the L1 latency 138m5.ticks.setGlobalFrequency('1ns') 139 140# instantiate configuration 141m5.instantiate() 142 143# simulate until program terminates 144exit_event = m5.simulate(options.maxtick) 145 146print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() |