1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 111 unchanged lines hidden (view full) ---

120# artifical delay is randomly inserted on messages
121#
122system.ruby.randomization = True
123
124for ruby_port in system.ruby._cpu_ports:
125 #
126 # Tie the ruby tester ports to the ruby cpu read and write ports
127 #
128 if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
129 tester.cpuInstDataPort = ruby_port.slave
130 elif ruby_port.support_data_reqs:
131 tester.cpuDataPort = ruby_port.slave
132 elif ruby_port.support_inst_reqs:
133 tester.cpuInstPort = ruby_port.slave
134
135 # Do not automatically retry stalled Ruby requests
136 ruby_port.no_retry_on_stall = True
137
138 #
139 # Tell each sequencer this is the ruby tester so that it
140 # copies the subblock back to the checker
141 #
142 ruby_port.using_ruby_tester = True
143
144# -----------------------
145# run simulation

--- 15 unchanged lines hidden ---