ruby_mem_test.py (9790:ccc428657233) | ruby_mem_test.py (9793:6e6cefc1db1f) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 93 unchanged lines hidden (view full) --- 102 percent_uncacheable = 0, 103 progress_interval = options.progress, 104 suppress_func_warnings = options.suppress_func_warnings) \ 105 for i in xrange(options.num_cpus) ] 106 107system = System(cpu = cpus, 108 funcmem = SimpleMemory(in_addr_map = False), 109 funcbus = NoncoherentBus(), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 93 unchanged lines hidden (view full) --- 102 percent_uncacheable = 0, 103 progress_interval = options.progress, 104 suppress_func_warnings = options.suppress_func_warnings) \ 105 for i in xrange(options.num_cpus) ] 106 107system = System(cpu = cpus, 108 funcmem = SimpleMemory(in_addr_map = False), 109 funcbus = NoncoherentBus(), |
110 physmem = SimpleMemory()) 111system.clock = options.sys_clock | 110 physmem = SimpleMemory(), 111 clk_domain = SrcClockDomain(clock = options.sys_clock)) |
112 113if options.num_dmas > 0: 114 dmas = [ MemTest(atomic = False, 115 max_loads = options.maxloads, 116 issue_dmas = True, 117 percent_functional = 0, 118 percent_uncacheable = 0, 119 progress_interval = options.progress, --- 4 unchanged lines hidden (view full) --- 124else: 125 dmas = [] 126 127dma_ports = [] 128for (i, dma) in enumerate(dmas): 129 dma_ports.append(dma.test) 130Ruby.create_system(options, system, dma_ports = dma_ports) 131 | 112 113if options.num_dmas > 0: 114 dmas = [ MemTest(atomic = False, 115 max_loads = options.maxloads, 116 issue_dmas = True, 117 percent_functional = 0, 118 percent_uncacheable = 0, 119 progress_interval = options.progress, --- 4 unchanged lines hidden (view full) --- 124else: 125 dmas = [] 126 127dma_ports = [] 128for (i, dma) in enumerate(dmas): 129 dma_ports.append(dma.test) 130Ruby.create_system(options, system, dma_ports = dma_ports) 131 |
132# Create a seperate clock domain for Ruby 133system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) 134 |
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132# 133# The tester is most effective when randomization is turned on and 134# artifical delay is randomly inserted on messages 135# 136system.ruby.randomization = True 137 138assert(len(cpus) == len(system.ruby._cpu_ruby_ports)) 139 --- 46 unchanged lines hidden --- | 135# 136# The tester is most effective when randomization is turned on and 137# artifical delay is randomly inserted on messages 138# 139system.ruby.randomization = True 140 141assert(len(cpus) == len(system.ruby._cpu_ruby_ports)) 142 --- 46 unchanged lines hidden --- |