ruby_mem_test.py (9100:3caf131d7a95) | ruby_mem_test.py (9120:48eeef8a0997) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 93 unchanged lines hidden (view full) --- 102 percent_functional = options.functional, 103 percent_uncacheable = 0, 104 progress_interval = options.progress, 105 suppress_func_warnings = options.suppress_func_warnings) \ 106 for i in xrange(options.num_cpus) ] 107 108system = System(cpu = cpus, 109 funcmem = SimpleMemory(in_addr_map = False), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 93 unchanged lines hidden (view full) --- 102 percent_functional = options.functional, 103 percent_uncacheable = 0, 104 progress_interval = options.progress, 105 suppress_func_warnings = options.suppress_func_warnings) \ 106 for i in xrange(options.num_cpus) ] 107 108system = System(cpu = cpus, 109 funcmem = SimpleMemory(in_addr_map = False), |
110 funcbus = NoncoherentBus(), |
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110 physmem = SimpleMemory()) 111 112if options.num_dmas > 0: 113 dmas = [ MemTest(atomic = False, 114 max_loads = options.maxloads, 115 issue_dmas = True, 116 percent_functional = 0, 117 percent_uncacheable = 0, --- 18 unchanged lines hidden (view full) --- 136 137assert(len(cpus) == len(system.ruby._cpu_ruby_ports)) 138 139for (i, cpu) in enumerate(cpus): 140 # 141 # Tie the cpu memtester ports to the correct system ports 142 # 143 cpu.test = system.ruby._cpu_ruby_ports[i].slave | 111 physmem = SimpleMemory()) 112 113if options.num_dmas > 0: 114 dmas = [ MemTest(atomic = False, 115 max_loads = options.maxloads, 116 issue_dmas = True, 117 percent_functional = 0, 118 percent_uncacheable = 0, --- 18 unchanged lines hidden (view full) --- 137 138assert(len(cpus) == len(system.ruby._cpu_ruby_ports)) 139 140for (i, cpu) in enumerate(cpus): 141 # 142 # Tie the cpu memtester ports to the correct system ports 143 # 144 cpu.test = system.ruby._cpu_ruby_ports[i].slave |
144 cpu.functional = system.funcmem.port | 145 cpu.functional = system.funcbus.slave |
145 146 # 147 # Since the memtester is incredibly bursty, increase the deadlock 148 # threshold to 5 million cycles 149 # 150 system.ruby._cpu_ruby_ports[i].deadlock_threshold = 5000000 151 152 # 153 # Ruby doesn't need the backing image of memory when running with 154 # the tester. 155 # 156 system.ruby._cpu_ruby_ports[i].access_phys_mem = False 157 158for (i, dma) in enumerate(dmas): 159 # 160 # Tie the dma memtester ports to the correct functional port 161 # Note that the test port has already been connected to the dma_sequencer 162 # | 146 147 # 148 # Since the memtester is incredibly bursty, increase the deadlock 149 # threshold to 5 million cycles 150 # 151 system.ruby._cpu_ruby_ports[i].deadlock_threshold = 5000000 152 153 # 154 # Ruby doesn't need the backing image of memory when running with 155 # the tester. 156 # 157 system.ruby._cpu_ruby_ports[i].access_phys_mem = False 158 159for (i, dma) in enumerate(dmas): 160 # 161 # Tie the dma memtester ports to the correct functional port 162 # Note that the test port has already been connected to the dma_sequencer 163 # |
163 dma.functional = system.funcmem.port | 164 dma.functional = system.funcbus.slave |
164 | 165 |
166# connect reference memory to funcbus 167system.funcbus.master = system.funcmem.port 168 |
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165# ----------------------- 166# run simulation 167# ----------------------- 168 169root = Root( full_system = False, system = system ) 170root.system.mem_mode = 'timing' 171 172# Not much point in this being higher than the L1 latency 173m5.ticks.setGlobalFrequency('1ns') 174 175# instantiate configuration 176m5.instantiate() 177 178# simulate until program terminates 179exit_event = m5.simulate(options.maxtick) 180 181print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() | 169# ----------------------- 170# run simulation 171# ----------------------- 172 173root = Root( full_system = False, system = system ) 174root.system.mem_mode = 'timing' 175 176# Not much point in this being higher than the L1 latency 177m5.ticks.setGlobalFrequency('1ns') 178 179# instantiate configuration 180m5.instantiate() 181 182# simulate until program terminates 183exit_event = m5.simulate(options.maxtick) 184 185print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() |