ruby_mem_test.py (11688:725fef71f376) | ruby_mem_test.py (12564:2778478ca882) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 14 unchanged lines hidden (view full) --- 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29# Brad Beckmann 30 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 14 unchanged lines hidden (view full) --- 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29# Brad Beckmann 30 |
31from __future__ import print_function 32 |
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31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from m5.util import addToPath 35import os, optparse, sys 36 37addToPath('../') 38 --- 37 unchanged lines hidden (view full) --- 76options.l2_size="512B" 77options.l3_size="1kB" 78options.l1d_assoc=2 79options.l1i_assoc=2 80options.l2_assoc=2 81options.l3_assoc=2 82 83if args: | 33import m5 34from m5.objects import * 35from m5.defines import buildEnv 36from m5.util import addToPath 37import os, optparse, sys 38 39addToPath('../') 40 --- 37 unchanged lines hidden (view full) --- 78options.l2_size="512B" 79options.l3_size="1kB" 80options.l1d_assoc=2 81options.l1i_assoc=2 82options.l2_assoc=2 83options.l3_assoc=2 84 85if args: |
84 print "Error: script doesn't take any positional arguments" | 86 print("Error: script doesn't take any positional arguments") |
85 sys.exit(1) 86 87block_size = 64 88 89if options.num_cpus > block_size: | 87 sys.exit(1) 88 89block_size = 64 90 91if options.num_cpus > block_size: |
90 print "Error: Number of testers %d limited to %d because of false sharing" \ 91 % (options.num_cpus, block_size) | 92 print("Error: Number of testers %d limited to %d because of false sharing" 93 % (options.num_cpus, block_size)) |
92 sys.exit(1) 93 94# 95# Currently ruby does not support atomic or uncacheable accesses 96# 97cpus = [ MemTest(atomic = False, 98 max_loads = options.maxloads, 99 issue_dmas = False, --- 78 unchanged lines hidden (view full) --- 178m5.ticks.setGlobalFrequency('1ns') 179 180# instantiate configuration 181m5.instantiate() 182 183# simulate until program terminates 184exit_event = m5.simulate(options.abs_max_tick) 185 | 94 sys.exit(1) 95 96# 97# Currently ruby does not support atomic or uncacheable accesses 98# 99cpus = [ MemTest(atomic = False, 100 max_loads = options.maxloads, 101 issue_dmas = False, --- 78 unchanged lines hidden (view full) --- 180m5.ticks.setGlobalFrequency('1ns') 181 182# instantiate configuration 183m5.instantiate() 184 185# simulate until program terminates 186exit_event = m5.simulate(options.abs_max_tick) 187 |
186print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() | 188print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()) |