| ruby_mem_test.py (10405:7a618c07e663) | ruby_mem_test.py (10519:7a3ad4b09ce4) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 114 unchanged lines hidden (view full) --- 123 for i in xrange(options.num_dmas) ] 124 system.dma_devices = dmas 125else: 126 dmas = [] 127 128dma_ports = [] 129for (i, dma) in enumerate(dmas): 130 dma_ports.append(dma.test) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 114 unchanged lines hidden (view full) --- 123 for i in xrange(options.num_dmas) ] 124 system.dma_devices = dmas 125else: 126 dmas = [] 127 128dma_ports = [] 129for (i, dma) in enumerate(dmas): 130 dma_ports.append(dma.test) |
| 131Ruby.create_system(options, system, dma_ports = dma_ports) | 131Ruby.create_system(options, False, system, dma_ports = dma_ports) |
| 132 133# Create a top-level voltage domain and clock domain 134system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 135system.clk_domain = SrcClockDomain(clock = options.sys_clock, 136 voltage_domain = system.voltage_domain) 137# Create a seperate clock domain for Ruby 138system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 139 voltage_domain = system.voltage_domain) --- 14 unchanged lines hidden (view full) --- 154 cpu.functional = system.funcbus.slave 155 156 # 157 # Since the memtester is incredibly bursty, increase the deadlock 158 # threshold to 5 million cycles 159 # 160 system.ruby._cpu_ports[i].deadlock_threshold = 5000000 161 | 132 133# Create a top-level voltage domain and clock domain 134system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 135system.clk_domain = SrcClockDomain(clock = options.sys_clock, 136 voltage_domain = system.voltage_domain) 137# Create a seperate clock domain for Ruby 138system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 139 voltage_domain = system.voltage_domain) --- 14 unchanged lines hidden (view full) --- 154 cpu.functional = system.funcbus.slave 155 156 # 157 # Since the memtester is incredibly bursty, increase the deadlock 158 # threshold to 5 million cycles 159 # 160 system.ruby._cpu_ports[i].deadlock_threshold = 5000000 161 |
| 162 # 163 # Ruby doesn't need the backing image of memory when running with 164 # the tester. 165 # 166 system.ruby._cpu_ports[i].access_phys_mem = False 167 | |
| 168for (i, dma) in enumerate(dmas): 169 # 170 # Tie the dma memtester ports to the correct functional port 171 # Note that the test port has already been connected to the dma_sequencer 172 # 173 dma.functional = system.funcbus.slave 174 175# connect reference memory to funcbus --- 19 unchanged lines hidden --- | 162for (i, dma) in enumerate(dmas): 163 # 164 # Tie the dma memtester ports to the correct functional port 165 # Note that the test port has already been connected to the dma_sequencer 166 # 167 dma.functional = system.funcbus.slave 168 169# connect reference memory to funcbus --- 19 unchanged lines hidden --- |