1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 148 unchanged lines hidden (view full) --- 157 # Note that the test port has already been connected to the dma_sequencer 158 # 159 dma.functional = system.funcmem.port 160 161# ----------------------- 162# run simulation 163# ----------------------- 164 |
165root = Root( full_system = False, system = system ) |
166root.system.mem_mode = 'timing' 167 168# Not much point in this being higher than the L1 latency 169m5.ticks.setGlobalFrequency('1ns') 170 171# instantiate configuration 172m5.instantiate() 173 174# simulate until program terminates 175exit_event = m5.simulate(options.maxtick) 176 177print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() |