1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 82 unchanged lines hidden (view full) --- 91if options.num_cpus > block_size: 92 print("Error: Number of testers %d limited to %d because of false sharing" 93 % (options.num_cpus, block_size)) 94 sys.exit(1) 95 96# 97# Currently ruby does not support atomic or uncacheable accesses 98# |
99cpus = [ MemTest(max_loads = options.maxloads, |
100 percent_functional = options.functional, 101 percent_uncacheable = 0, 102 progress_interval = options.progress, 103 suppress_func_warnings = options.suppress_func_warnings) \ 104 for i in xrange(options.num_cpus) ] 105 106system = System(cpu = cpus, |
107 clk_domain = SrcClockDomain(clock = options.sys_clock), 108 mem_ranges = [AddrRange(options.mem_size)]) 109 110if options.num_dmas > 0: |
111 dmas = [ MemTest(max_loads = options.maxloads, |
112 percent_functional = 0, 113 percent_uncacheable = 0, 114 progress_interval = options.progress, 115 suppress_func_warnings = 116 not options.suppress_func_warnings) \ 117 for i in xrange(options.num_dmas) ] 118 system.dma_devices = dmas 119else: --- 19 unchanged lines hidden (view full) --- 139system.ruby.randomization = True 140 141assert(len(cpus) == len(system.ruby._cpu_ports)) 142 143for (i, cpu) in enumerate(cpus): 144 # 145 # Tie the cpu memtester ports to the correct system ports 146 # |
147 cpu.port = system.ruby._cpu_ports[i].slave |
148 149 # 150 # Since the memtester is incredibly bursty, increase the deadlock 151 # threshold to 5 million cycles 152 # 153 system.ruby._cpu_ports[i].deadlock_threshold = 5000000 154 |
155# ----------------------- 156# run simulation 157# ----------------------- 158 159root = Root( full_system = False, system = system ) 160root.system.mem_mode = 'timing' 161 162# Not much point in this being higher than the L1 latency 163m5.ticks.setGlobalFrequency('1ns') 164 165# instantiate configuration 166m5.instantiate() 167 168# simulate until program terminates 169exit_event = m5.simulate(options.abs_max_tick) 170 171print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()) |