1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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91if options.num_cpus > block_size:
92 print("Error: Number of testers %d limited to %d because of false sharing"
93 % (options.num_cpus, block_size))
94 sys.exit(1)
95
96#
97# Currently ruby does not support atomic or uncacheable accesses
98#
99cpus = [ MemTest(atomic = False,
100 max_loads = options.maxloads,
101 issue_dmas = False,
102 percent_functional = options.functional,
103 percent_uncacheable = 0,
104 progress_interval = options.progress,
105 suppress_func_warnings = options.suppress_func_warnings) \
106 for i in xrange(options.num_cpus) ]
107
108system = System(cpu = cpus,
109 funcmem = SimpleMemory(in_addr_map = False),
110 funcbus = IOXBar(),
111 clk_domain = SrcClockDomain(clock = options.sys_clock),
112 mem_ranges = [AddrRange(options.mem_size)])
113
114if options.num_dmas > 0:
115 dmas = [ MemTest(atomic = False,
116 max_loads = options.maxloads,
117 issue_dmas = True,
118 percent_functional = 0,
119 percent_uncacheable = 0,
120 progress_interval = options.progress,
121 suppress_func_warnings =
122 not options.suppress_func_warnings) \
123 for i in xrange(options.num_dmas) ]
124 system.dma_devices = dmas
125else:

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145system.ruby.randomization = True
146
147assert(len(cpus) == len(system.ruby._cpu_ports))
148
149for (i, cpu) in enumerate(cpus):
150 #
151 # Tie the cpu memtester ports to the correct system ports
152 #
153 cpu.test = system.ruby._cpu_ports[i].slave
154 cpu.functional = system.funcbus.slave
155
156 #
157 # Since the memtester is incredibly bursty, increase the deadlock
158 # threshold to 5 million cycles
159 #
160 system.ruby._cpu_ports[i].deadlock_threshold = 5000000
161
162for (i, dma) in enumerate(dmas):
163 #
164 # Tie the dma memtester ports to the correct functional port
165 # Note that the test port has already been connected to the dma_sequencer
166 #
167 dma.functional = system.funcbus.slave
168
169# connect reference memory to funcbus
170system.funcbus.master = system.funcmem.port
171
172# -----------------------
173# run simulation
174# -----------------------
175
176root = Root( full_system = False, system = system )
177root.system.mem_mode = 'timing'
178
179# Not much point in this being higher than the L1 latency
180m5.ticks.setGlobalFrequency('1ns')
181
182# instantiate configuration
183m5.instantiate()
184
185# simulate until program terminates
186exit_event = m5.simulate(options.abs_max_tick)
187
188print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())