1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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102 percent_functional = options.functional,
103 percent_uncacheable = 0,
104 progress_interval = options.progress,
105 suppress_func_warnings = options.suppress_func_warnings) \
106 for i in xrange(options.num_cpus) ]
107
108system = System(cpu = cpus,
109 funcmem = SimpleMemory(in_addr_map = False),
110 funcbus = NoncoherentBus(),
111 physmem = SimpleMemory())
112
113if options.num_dmas > 0:
114 dmas = [ MemTest(atomic = False,
115 max_loads = options.maxloads,
116 issue_dmas = True,
117 percent_functional = 0,
118 percent_uncacheable = 0,

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137
138assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
139
140for (i, cpu) in enumerate(cpus):
141 #
142 # Tie the cpu memtester ports to the correct system ports
143 #
144 cpu.test = system.ruby._cpu_ruby_ports[i].slave
145 cpu.functional = system.funcbus.slave
146
147 #
148 # Since the memtester is incredibly bursty, increase the deadlock
149 # threshold to 5 million cycles
150 #
151 system.ruby._cpu_ruby_ports[i].deadlock_threshold = 5000000
152
153 #
154 # Ruby doesn't need the backing image of memory when running with
155 # the tester.
156 #
157 system.ruby._cpu_ruby_ports[i].access_phys_mem = False
158
159for (i, dma) in enumerate(dmas):
160 #
161 # Tie the dma memtester ports to the correct functional port
162 # Note that the test port has already been connected to the dma_sequencer
163 #
164 dma.functional = system.funcbus.slave
165
166# connect reference memory to funcbus
167system.funcbus.master = system.funcmem.port
168
169# -----------------------
170# run simulation
171# -----------------------
172
173root = Root( full_system = False, system = system )
174root.system.mem_mode = 'timing'
175
176# Not much point in this being higher than the L1 latency
177m5.ticks.setGlobalFrequency('1ns')
178
179# instantiate configuration
180m5.instantiate()
181
182# simulate until program terminates
183exit_event = m5.simulate(options.maxtick)
184
185print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()