| memcheck.py (12564:2778478ca882) | memcheck.py (13731:67cd980cb20f) |
|---|---|
| 1# Copyright (c) 2015-2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 232 unchanged lines hidden (view full) --- 241 # Create a subsystem to contain the crossbar and caches, and 242 # any testers 243 subsys = SubSystem() 244 setattr(system, 'l%dsubsys%d' % (level, index), subsys) 245 246 # The levels are indexing backwards through the list 247 ntesters = testerspec[len(cachespec) - level] 248 | 1# Copyright (c) 2015-2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 232 unchanged lines hidden (view full) --- 241 # Create a subsystem to contain the crossbar and caches, and 242 # any testers 243 subsys = SubSystem() 244 setattr(system, 'l%dsubsys%d' % (level, index), subsys) 245 246 # The levels are indexing backwards through the list 247 ntesters = testerspec[len(cachespec) - level] 248 |
| 249 testers = [proto_tester() for i in xrange(ntesters)] | 249 testers = [proto_tester() for i in range(ntesters)] |
| 250 checkers = [MemCheckerMonitor(memchecker = system.memchecker) \ | 250 checkers = [MemCheckerMonitor(memchecker = system.memchecker) \ |
| 251 for i in xrange(ntesters)] | 251 for i in range(ntesters)] |
| 252 if ntesters: 253 subsys.tester = testers 254 subsys.checkers = checkers 255 256 if level != 0: 257 # Create a crossbar and add it to the subsystem, note that 258 # we do this even with a single element on this level 259 xbar = L2XBar(width = 32) 260 subsys.xbar = xbar 261 if next_cache: 262 xbar.master = next_cache.cpu_side 263 264 # Create and connect the caches, both the ones fanning out 265 # to create the tree, and the ones used to connect testers 266 # on this level | 252 if ntesters: 253 subsys.tester = testers 254 subsys.checkers = checkers 255 256 if level != 0: 257 # Create a crossbar and add it to the subsystem, note that 258 # we do this even with a single element on this level 259 xbar = L2XBar(width = 32) 260 subsys.xbar = xbar 261 if next_cache: 262 xbar.master = next_cache.cpu_side 263 264 # Create and connect the caches, both the ones fanning out 265 # to create the tree, and the ones used to connect testers 266 # on this level |
| 267 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])] 268 tester_caches = [proto_l1() for i in xrange(ntesters)] | 267 tree_caches = [prototypes[0]() for i in range(ncaches[0])] 268 tester_caches = [proto_l1() for i in range(ntesters)] |
| 269 270 subsys.cache = tester_caches + tree_caches 271 for cache in tree_caches: 272 cache.mem_side = xbar.slave 273 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 274 for tester, checker, cache in zip(testers, checkers, tester_caches): 275 tester.port = checker.slave 276 checker.master = cache.cpu_side --- 44 unchanged lines hidden --- | 269 270 subsys.cache = tester_caches + tree_caches 271 for cache in tree_caches: 272 cache.mem_side = xbar.slave 273 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 274 for tester, checker, cache in zip(testers, checkers, tester_caches): 275 tester.port = checker.slave 276 checker.master = cache.cpu_side --- 44 unchanged lines hidden --- |