| memcheck.py (10705:c6cb94a14fea) | memcheck.py (10720:67b3e74de9ae) |
|---|---|
| 1# Copyright (c) 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 229 unchanged lines hidden (view full) --- 238 for i in xrange(ntesters)] 239 if ntesters: 240 subsys.tester = testers 241 subsys.checkers = checkers 242 243 if level != 0: 244 # Create a crossbar and add it to the subsystem, note that 245 # we do this even with a single element on this level | 1# Copyright (c) 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 229 unchanged lines hidden (view full) --- 238 for i in xrange(ntesters)] 239 if ntesters: 240 subsys.tester = testers 241 subsys.checkers = checkers 242 243 if level != 0: 244 # Create a crossbar and add it to the subsystem, note that 245 # we do this even with a single element on this level |
| 246 xbar = CoherentXBar(width = 32) | 246 xbar = L2XBar(width = 32) |
| 247 subsys.xbar = xbar 248 if next_cache: 249 xbar.master = next_cache.cpu_side 250 251 # Create and connect the caches, both the ones fanning out 252 # to create the tree, and the ones used to connect testers 253 # on this level 254 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])] --- 9 unchanged lines hidden (view full) --- 264 cache.mem_side = xbar.slave 265 else: 266 if not next_cache: 267 print "Error: No next-level cache at top level" 268 sys.exit(1) 269 270 if ntesters > 1: 271 # Create a crossbar and add it to the subsystem | 247 subsys.xbar = xbar 248 if next_cache: 249 xbar.master = next_cache.cpu_side 250 251 # Create and connect the caches, both the ones fanning out 252 # to create the tree, and the ones used to connect testers 253 # on this level 254 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])] --- 9 unchanged lines hidden (view full) --- 264 cache.mem_side = xbar.slave 265 else: 266 if not next_cache: 267 print "Error: No next-level cache at top level" 268 sys.exit(1) 269 270 if ntesters > 1: 271 # Create a crossbar and add it to the subsystem |
| 272 xbar = CoherentXBar(width = 32) | 272 xbar = L2XBar(width = 32) |
| 273 subsys.xbar = xbar 274 xbar.master = next_cache.cpu_side 275 for tester, checker in zip(testers, checkers): 276 tester.port = checker.slave 277 checker.master = xbar.slave 278 else: 279 # Single tester 280 testers[0].port = checkers[0].slave --- 26 unchanged lines hidden --- | 273 subsys.xbar = xbar 274 xbar.master = next_cache.cpu_side 275 for tester, checker in zip(testers, checkers): 276 tester.port = checker.slave 277 checker.master = xbar.slave 278 else: 279 # Single tester 280 testers[0].port = checkers[0].slave --- 26 unchanged lines hidden --- |