1# Copyright (c) 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ron Dreslinski
40# Andreas Hansson
41
42import optparse
43import sys
44
45import m5
46from m5.objects import *
47
48parser = optparse.OptionParser()
49
50parser.add_option("-a", "--atomic", action="store_true",
51 help="Use atomic (non-timing) mode")
52parser.add_option("-b", "--blocking", action="store_true",
53 help="Use blocking caches")
54parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
55 metavar="T",
56 help="Stop after T ticks")
57parser.add_option("-p", "--prefetchers", action="store_true",
58 help="Use prefetchers")
59parser.add_option("-s", "--stridepref", action="store_true",
60 help="Use strided prefetchers")
61
62# This example script has a lot in common with the memtest.py in that
63# it is designed to stress tests the memory system. However, this
64# script uses oblivious traffic generators to create the stimuli, and
65# couples them with memcheckers to verify that the data read matches
66# the allowed outcomes. Just like memtest.py, the traffic generators
67# and checkers are placed in a tree topology. At the bottom of the
68# tree is a shared memory, and then at each level a number of
69# generators and checkers are attached, along with a number of caches
70# that them selves fan out to subtrees of generators and caches. Thus,
71# it is possible to create a system with arbitrarily deep cache
72# hierarchies, sharing or no sharing of caches, and generators not
73# only at the L1s, but also at the L2s, L3s etc.
74#
75# The tree specification consists of two colon-separated lists of one
76# or more integers, one for the caches, and one for the
77# testers/generators. The first integer is the number of
78# caches/testers closest to main memory. Each cache then fans out to a
79# subtree. The last integer in the list is the number of
80# caches/testers associated with the uppermost level of memory. The
81# other integers (if any) specify the number of caches/testers
82# connected at each level of the crossbar hierarchy. The tester string
83# should have one element more than the cache string as there should
84# always be testers attached to the uppermost caches.
85#
86# Since this script tests actual sharing, there is also a possibility
87# to stress prefetching and the interaction between prefetchers and
88# caches. The traffic generators switch between random address streams
89# and linear address streams to ensure that the prefetchers will
90# trigger. By default prefetchers are off.
91
92parser.add_option("-c", "--caches", type="string", default="3:2",
93 help="Colon-separated cache hierarchy specification, "
94 "see script comments for details "
95 "[default: %default]")
96parser.add_option("-t", "--testers", type="string", default="1:0:2",
97 help="Colon-separated tester hierarchy specification, "
98 "see script comments for details "
99 "[default: %default]")
100parser.add_option("--sys-clock", action="store", type="string",
101 default='1GHz',
102 help = """Top-level clock for blocks running at system
103 speed""")
104
105(options, args) = parser.parse_args()
106
107if args:
108 print "Error: script doesn't take any positional arguments"
109 sys.exit(1)
110
111# Start by parsing the command line options and do some basic sanity
112# checking
113try:
114 cachespec = [int(x) for x in options.caches.split(':')]
115 testerspec = [int(x) for x in options.testers.split(':')]
116except:
117 print "Error: Unable to parse caches or testers option"
118 sys.exit(1)
119
120if len(cachespec) < 1:
121 print "Error: Must have at least one level of caches"
122 sys.exit(1)
123
124if len(cachespec) != len(testerspec) - 1:
125 print "Error: Testers must have one element more than caches"
126 sys.exit(1)
127
128if testerspec[-1] == 0:
129 print "Error: Must have testers at the uppermost level"
130 sys.exit(1)
131
132for t in testerspec:
133 if t < 0:
134 print "Error: Cannot have a negative number of testers"
135 sys.exit(1)
136
137for c in cachespec:
138 if c < 1:
139 print "Error: Must have 1 or more caches at each level"
140 sys.exit(1)
141
142# Determine the tester multiplier for each level as the string
143# elements are per subsystem and it fans out
144multiplier = [1]
145for c in cachespec:
146 if c < 1:
147 print "Error: Must have at least one cache per level"
148 multiplier.append(multiplier[-1] * c)
149
150numtesters = 0
151for t, m in zip(testerspec, multiplier):
152 numtesters += t * m
153
154# Define a prototype L1 cache that we scale for all successive levels
| 1# Copyright (c) 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ron Dreslinski
40# Andreas Hansson
41
42import optparse
43import sys
44
45import m5
46from m5.objects import *
47
48parser = optparse.OptionParser()
49
50parser.add_option("-a", "--atomic", action="store_true",
51 help="Use atomic (non-timing) mode")
52parser.add_option("-b", "--blocking", action="store_true",
53 help="Use blocking caches")
54parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
55 metavar="T",
56 help="Stop after T ticks")
57parser.add_option("-p", "--prefetchers", action="store_true",
58 help="Use prefetchers")
59parser.add_option("-s", "--stridepref", action="store_true",
60 help="Use strided prefetchers")
61
62# This example script has a lot in common with the memtest.py in that
63# it is designed to stress tests the memory system. However, this
64# script uses oblivious traffic generators to create the stimuli, and
65# couples them with memcheckers to verify that the data read matches
66# the allowed outcomes. Just like memtest.py, the traffic generators
67# and checkers are placed in a tree topology. At the bottom of the
68# tree is a shared memory, and then at each level a number of
69# generators and checkers are attached, along with a number of caches
70# that them selves fan out to subtrees of generators and caches. Thus,
71# it is possible to create a system with arbitrarily deep cache
72# hierarchies, sharing or no sharing of caches, and generators not
73# only at the L1s, but also at the L2s, L3s etc.
74#
75# The tree specification consists of two colon-separated lists of one
76# or more integers, one for the caches, and one for the
77# testers/generators. The first integer is the number of
78# caches/testers closest to main memory. Each cache then fans out to a
79# subtree. The last integer in the list is the number of
80# caches/testers associated with the uppermost level of memory. The
81# other integers (if any) specify the number of caches/testers
82# connected at each level of the crossbar hierarchy. The tester string
83# should have one element more than the cache string as there should
84# always be testers attached to the uppermost caches.
85#
86# Since this script tests actual sharing, there is also a possibility
87# to stress prefetching and the interaction between prefetchers and
88# caches. The traffic generators switch between random address streams
89# and linear address streams to ensure that the prefetchers will
90# trigger. By default prefetchers are off.
91
92parser.add_option("-c", "--caches", type="string", default="3:2",
93 help="Colon-separated cache hierarchy specification, "
94 "see script comments for details "
95 "[default: %default]")
96parser.add_option("-t", "--testers", type="string", default="1:0:2",
97 help="Colon-separated tester hierarchy specification, "
98 "see script comments for details "
99 "[default: %default]")
100parser.add_option("--sys-clock", action="store", type="string",
101 default='1GHz',
102 help = """Top-level clock for blocks running at system
103 speed""")
104
105(options, args) = parser.parse_args()
106
107if args:
108 print "Error: script doesn't take any positional arguments"
109 sys.exit(1)
110
111# Start by parsing the command line options and do some basic sanity
112# checking
113try:
114 cachespec = [int(x) for x in options.caches.split(':')]
115 testerspec = [int(x) for x in options.testers.split(':')]
116except:
117 print "Error: Unable to parse caches or testers option"
118 sys.exit(1)
119
120if len(cachespec) < 1:
121 print "Error: Must have at least one level of caches"
122 sys.exit(1)
123
124if len(cachespec) != len(testerspec) - 1:
125 print "Error: Testers must have one element more than caches"
126 sys.exit(1)
127
128if testerspec[-1] == 0:
129 print "Error: Must have testers at the uppermost level"
130 sys.exit(1)
131
132for t in testerspec:
133 if t < 0:
134 print "Error: Cannot have a negative number of testers"
135 sys.exit(1)
136
137for c in cachespec:
138 if c < 1:
139 print "Error: Must have 1 or more caches at each level"
140 sys.exit(1)
141
142# Determine the tester multiplier for each level as the string
143# elements are per subsystem and it fans out
144multiplier = [1]
145for c in cachespec:
146 if c < 1:
147 print "Error: Must have at least one cache per level"
148 multiplier.append(multiplier[-1] * c)
149
150numtesters = 0
151for t, m in zip(testerspec, multiplier):
152 numtesters += t * m
153
154# Define a prototype L1 cache that we scale for all successive levels
|
158
159if options.blocking:
160 proto_l1.mshrs = 1
161else:
162 proto_l1.mshrs = 4
163
164if options.prefetchers:
165 proto_l1.prefetcher = TaggedPrefetcher()
166elif options.stridepref:
167 proto_l1.prefetcher = StridePrefetcher()
168
169cache_proto = [proto_l1]
170
171# Now add additional cache levels (if any) by scaling L1 params, the
172# first element is Ln, and the last element L1
173for scale in cachespec[:-1]:
174 # Clone previous level and update params
175 prev = cache_proto[0]
176 next = prev()
177 next.size = prev.size * scale
178 next.hit_latency = prev.hit_latency * 10
179 next.response_latency = prev.response_latency * 10
180 next.assoc = prev.assoc * scale
181 next.mshrs = prev.mshrs * scale
182 cache_proto.insert(0, next)
183
184# Create a config to be used by all the traffic generators
185cfg_file_name = "configs/example/memcheck.cfg"
186cfg_file = open(cfg_file_name, 'w')
187
188# Three states, with random, linear and idle behaviours. The random
189# and linear states access memory in the range [0 : 16 Mbyte] with 8
190# byte accesses.
191cfg_file.write("STATE 0 10000000 RANDOM 65 0 16777216 8 50000 150000 0\n")
192cfg_file.write("STATE 1 10000000 LINEAR 65 0 16777216 8 50000 150000 0\n")
193cfg_file.write("STATE 2 10000000 IDLE\n")
194cfg_file.write("INIT 0\n")
195cfg_file.write("TRANSITION 0 1 0.5\n")
196cfg_file.write("TRANSITION 0 2 0.5\n")
197cfg_file.write("TRANSITION 1 0 0.5\n")
198cfg_file.write("TRANSITION 1 2 0.5\n")
199cfg_file.write("TRANSITION 2 0 0.5\n")
200cfg_file.write("TRANSITION 2 1 0.5\n")
201cfg_file.close()
202
203# Make a prototype for the tester to be used throughout
204proto_tester = TrafficGen(config_file = cfg_file_name)
205
206# Set up the system along with a DRAM controller
207system = System(physmem = DDR3_1600_x64())
208
209system.voltage_domain = VoltageDomain(voltage = '1V')
210
211system.clk_domain = SrcClockDomain(clock = options.sys_clock,
212 voltage_domain = system.voltage_domain)
213
214system.memchecker = MemChecker()
215
216# For each level, track the next subsys index to use
217next_subsys_index = [0] * (len(cachespec) + 1)
218
219# Recursive function to create a sub-tree of the cache and tester
220# hierarchy
221def make_cache_level(ncaches, prototypes, level, next_cache):
222 global next_subsys_index, proto_l1, testerspec, proto_tester
223
224 index = next_subsys_index[level]
225 next_subsys_index[level] += 1
226
227 # Create a subsystem to contain the crossbar and caches, and
228 # any testers
229 subsys = SubSystem()
230 setattr(system, 'l%dsubsys%d' % (level, index), subsys)
231
232 # The levels are indexing backwards through the list
233 ntesters = testerspec[len(cachespec) - level]
234
235 testers = [proto_tester() for i in xrange(ntesters)]
236 checkers = [MemCheckerMonitor(memchecker = system.memchecker) \
237 for i in xrange(ntesters)]
238 if ntesters:
239 subsys.tester = testers
240 subsys.checkers = checkers
241
242 if level != 0:
243 # Create a crossbar and add it to the subsystem, note that
244 # we do this even with a single element on this level
245 xbar = L2XBar(width = 32)
246 subsys.xbar = xbar
247 if next_cache:
248 xbar.master = next_cache.cpu_side
249
250 # Create and connect the caches, both the ones fanning out
251 # to create the tree, and the ones used to connect testers
252 # on this level
253 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
254 tester_caches = [proto_l1() for i in xrange(ntesters)]
255
256 subsys.cache = tester_caches + tree_caches
257 for cache in tree_caches:
258 cache.mem_side = xbar.slave
259 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
260 for tester, checker, cache in zip(testers, checkers, tester_caches):
261 tester.port = checker.slave
262 checker.master = cache.cpu_side
263 cache.mem_side = xbar.slave
264 else:
265 if not next_cache:
266 print "Error: No next-level cache at top level"
267 sys.exit(1)
268
269 if ntesters > 1:
270 # Create a crossbar and add it to the subsystem
271 xbar = L2XBar(width = 32)
272 subsys.xbar = xbar
273 xbar.master = next_cache.cpu_side
274 for tester, checker in zip(testers, checkers):
275 tester.port = checker.slave
276 checker.master = xbar.slave
277 else:
278 # Single tester
279 testers[0].port = checkers[0].slave
280 checkers[0].master = next_cache.cpu_side
281
282# Top level call to create the cache hierarchy, bottom up
283make_cache_level(cachespec, cache_proto, len(cachespec), None)
284
285# Connect the lowest level crossbar to the memory
286last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
287last_subsys.xbar.master = system.physmem.port
288
289root = Root(full_system = False, system = system)
290if options.atomic:
291 root.system.mem_mode = 'atomic'
292else:
293 root.system.mem_mode = 'timing'
294
295# The system port is never used in the tester so merely connect it
296# to avoid problems
297root.system.system_port = last_subsys.xbar.slave
298
299# Instantiate configuration
300m5.instantiate()
301
302# Simulate until program terminates
303exit_event = m5.simulate(options.maxtick)
304
305print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
| 158
159if options.blocking:
160 proto_l1.mshrs = 1
161else:
162 proto_l1.mshrs = 4
163
164if options.prefetchers:
165 proto_l1.prefetcher = TaggedPrefetcher()
166elif options.stridepref:
167 proto_l1.prefetcher = StridePrefetcher()
168
169cache_proto = [proto_l1]
170
171# Now add additional cache levels (if any) by scaling L1 params, the
172# first element is Ln, and the last element L1
173for scale in cachespec[:-1]:
174 # Clone previous level and update params
175 prev = cache_proto[0]
176 next = prev()
177 next.size = prev.size * scale
178 next.hit_latency = prev.hit_latency * 10
179 next.response_latency = prev.response_latency * 10
180 next.assoc = prev.assoc * scale
181 next.mshrs = prev.mshrs * scale
182 cache_proto.insert(0, next)
183
184# Create a config to be used by all the traffic generators
185cfg_file_name = "configs/example/memcheck.cfg"
186cfg_file = open(cfg_file_name, 'w')
187
188# Three states, with random, linear and idle behaviours. The random
189# and linear states access memory in the range [0 : 16 Mbyte] with 8
190# byte accesses.
191cfg_file.write("STATE 0 10000000 RANDOM 65 0 16777216 8 50000 150000 0\n")
192cfg_file.write("STATE 1 10000000 LINEAR 65 0 16777216 8 50000 150000 0\n")
193cfg_file.write("STATE 2 10000000 IDLE\n")
194cfg_file.write("INIT 0\n")
195cfg_file.write("TRANSITION 0 1 0.5\n")
196cfg_file.write("TRANSITION 0 2 0.5\n")
197cfg_file.write("TRANSITION 1 0 0.5\n")
198cfg_file.write("TRANSITION 1 2 0.5\n")
199cfg_file.write("TRANSITION 2 0 0.5\n")
200cfg_file.write("TRANSITION 2 1 0.5\n")
201cfg_file.close()
202
203# Make a prototype for the tester to be used throughout
204proto_tester = TrafficGen(config_file = cfg_file_name)
205
206# Set up the system along with a DRAM controller
207system = System(physmem = DDR3_1600_x64())
208
209system.voltage_domain = VoltageDomain(voltage = '1V')
210
211system.clk_domain = SrcClockDomain(clock = options.sys_clock,
212 voltage_domain = system.voltage_domain)
213
214system.memchecker = MemChecker()
215
216# For each level, track the next subsys index to use
217next_subsys_index = [0] * (len(cachespec) + 1)
218
219# Recursive function to create a sub-tree of the cache and tester
220# hierarchy
221def make_cache_level(ncaches, prototypes, level, next_cache):
222 global next_subsys_index, proto_l1, testerspec, proto_tester
223
224 index = next_subsys_index[level]
225 next_subsys_index[level] += 1
226
227 # Create a subsystem to contain the crossbar and caches, and
228 # any testers
229 subsys = SubSystem()
230 setattr(system, 'l%dsubsys%d' % (level, index), subsys)
231
232 # The levels are indexing backwards through the list
233 ntesters = testerspec[len(cachespec) - level]
234
235 testers = [proto_tester() for i in xrange(ntesters)]
236 checkers = [MemCheckerMonitor(memchecker = system.memchecker) \
237 for i in xrange(ntesters)]
238 if ntesters:
239 subsys.tester = testers
240 subsys.checkers = checkers
241
242 if level != 0:
243 # Create a crossbar and add it to the subsystem, note that
244 # we do this even with a single element on this level
245 xbar = L2XBar(width = 32)
246 subsys.xbar = xbar
247 if next_cache:
248 xbar.master = next_cache.cpu_side
249
250 # Create and connect the caches, both the ones fanning out
251 # to create the tree, and the ones used to connect testers
252 # on this level
253 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
254 tester_caches = [proto_l1() for i in xrange(ntesters)]
255
256 subsys.cache = tester_caches + tree_caches
257 for cache in tree_caches:
258 cache.mem_side = xbar.slave
259 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
260 for tester, checker, cache in zip(testers, checkers, tester_caches):
261 tester.port = checker.slave
262 checker.master = cache.cpu_side
263 cache.mem_side = xbar.slave
264 else:
265 if not next_cache:
266 print "Error: No next-level cache at top level"
267 sys.exit(1)
268
269 if ntesters > 1:
270 # Create a crossbar and add it to the subsystem
271 xbar = L2XBar(width = 32)
272 subsys.xbar = xbar
273 xbar.master = next_cache.cpu_side
274 for tester, checker in zip(testers, checkers):
275 tester.port = checker.slave
276 checker.master = xbar.slave
277 else:
278 # Single tester
279 testers[0].port = checkers[0].slave
280 checkers[0].master = next_cache.cpu_side
281
282# Top level call to create the cache hierarchy, bottom up
283make_cache_level(cachespec, cache_proto, len(cachespec), None)
284
285# Connect the lowest level crossbar to the memory
286last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
287last_subsys.xbar.master = system.physmem.port
288
289root = Root(full_system = False, system = system)
290if options.atomic:
291 root.system.mem_mode = 'atomic'
292else:
293 root.system.mem_mode = 'timing'
294
295# The system port is never used in the tester so merely connect it
296# to avoid problems
297root.system.system_port = last_subsys.xbar.slave
298
299# Instantiate configuration
300m5.instantiate()
301
302# Simulate until program terminates
303exit_event = m5.simulate(options.maxtick)
304
305print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
|