1import optparse
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2import sys
| 1import sys
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| 2import argparse
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3import subprocess
| 3import subprocess
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| 4from pprint import pprint
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4 5import m5 6from m5.objects import *
| 5 6import m5 7from m5.objects import *
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7from m5.util import addToPath
| 8from m5.util import *
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8 9addToPath('../') 10 11from common import MemConfig 12from common import HMC 13
| 9 10addToPath('../') 11 12from common import MemConfig 13from common import HMC 14
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14parser = optparse.OptionParser()
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15
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16# Use a HMC_2500_1x32 (1 channel, 32-bits wide) by default 17parser.add_option("--mem-type", type = "choice", default = "HMC_2500_1x32", 18 choices = MemConfig.mem_names(), 19 help = "type of memory to use")
| 16def add_options(parser): 17 parser.add_argument("--external-memory-system", default=0, action="store", 18 type=int, help="External memory system") 19 # TLM related options, currently optional in configs/common/MemConfig.py 20 parser.add_argument("--tlm-memory", action="store_true", help="use\ 21 external port for SystemC TLM co-simulation. Default:\ 22 no") 23 # Elastic traces related options, currently optional in 24 # configs/common/MemConfig.py 25 parser.add_argument("--elastic-trace-en", action="store_true", 26 help="enable capture of data dependency and\ 27 instruction fetch traces using elastic trace\ 28 probe.\nDefault: no") 29 # Options related to traffic generation 30 parser.add_argument("--num-tgen", default=4, action="store", type=int, 31 choices=[4], help="number of traffic generators.\ 32 Right now this script supports only 4.\nDefault: 4") 33 parser.add_argument("--tgen-cfg-file", 34 default="./configs/example/hmc_tgen.cfg", 35 type=str, help="Traffic generator(s) configuration\ 36 file. Note: this script uses the same configuration\ 37 file for all traffic generators")
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20
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21parser.add_option("--ranks", "-r", type = "int", default = 1, 22 help = "Number of ranks to iterate across")
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23
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24parser.add_option("--rd_perc", type ="int", default=100, 25 help = "Percentage of read commands") 26 27parser.add_option("--mode", type ="choice", default ="DRAM", 28 choices = ["DRAM", "DRAM_ROTATE", "RANDOM"], 29 help = "DRAM: Random traffic; \ 30 DRAM_ROTATE: Traffic rotating across banks and ranks" 31 ) 32 33parser.add_option("--addr_map", type ="int", default = 1, 34 help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo") 35 36parser.add_option("--arch", type = "choice", default = "distributed", 37 choices = ["same", "distributed", "mixed"], 38 help = "same: HMC-4 links with same range\ 39 distributed: HMC-4 links with distributed range\ 40 mixed: mixed with same & distributed range") 41 42parser.add_option("--linkaggr", type = "int", default = 0, 43 help = "1: enable link crossbar, 0: disable link crossbar") 44 45parser.add_option("--num_cross", type = "int", default = 4, 46 help = "1: number of crossbar in HMC=1;\ 47 4: number of crossbar = 4") 48 49parser.add_option("--tlm-memory", type = "string", 50 help="use external port for SystemC TLM cosimulation") 51 52parser.add_option("--elastic-trace-en", action ="store_true", 53 help = """Enable capture of data dependency and instruction 54 fetch traces using elastic trace probe.""") 55 56(options, args) = parser.parse_args() 57 58if args: 59 print "Error: script doesn't take any positional arguments" 60 sys.exit(1) 61 62system = System() 63system.clk_domain = SrcClockDomain(clock='100GHz', 64 voltage_domain= 65 VoltageDomain(voltage = '1V')) 66# Create additional crossbar for arch1 67if options.arch == "distributed" or options.arch == "mixed" : 68 system.membus = NoncoherentXBar( width=8 ) 69 system.membus.badaddr_responder = BadAddr() 70 system.membus.default = Self.badaddr_responder.pio 71 system.membus.width = 8 72 system.membus.frontend_latency = 3 73 system.membus.forward_latency = 4 74 system.membus.response_latency = 2 75 76 system.membus.clk_domain = SrcClockDomain(clock='100GHz', voltage_domain= 77 VoltageDomain(voltage = '1V')) 78 79# we are considering 4GB HMC device with following parameters
| 40# considering 4GB HMC device with following parameters
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80# hmc_device_size = '4GB'
| 41# hmc_device_size = '4GB'
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81# hmc_num_vaults = 16
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82# hmc_vault_size = '256MB' 83# hmc_stack_size = 8 84# hmc_bank_in_stack = 2 85# hmc_bank_size = '16MB' 86# hmc_bank_in_vault = 16
| 42# hmc_vault_size = '256MB' 43# hmc_stack_size = 8 44# hmc_bank_in_stack = 2 45# hmc_bank_size = '16MB' 46# hmc_bank_in_vault = 16
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| 47def build_system(options): 48 # create the system we are going to simulate 49 system = System() 50 # use timing mode for the interaction between master-slave ports 51 system.mem_mode = 'timing' 52 # set the clock fequency of the system 53 clk = '100GHz' 54 vd = VoltageDomain(voltage='1V') 55 system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd) 56 # add traffic generators to the system 57 system.tgen = [TrafficGen(config_file=options.tgen_cfg_file) for i in 58 xrange(options.num_tgen)] 59 # Config memory system with given HMC arch 60 MemConfig.config_mem(options, system) 61 # Connect the traffic generatiors 62 if options.arch == "distributed": 63 for i in xrange(options.num_tgen): 64 system.tgen[i].port = system.membus.slave 65 # connect the system port even if it is not used in this example 66 system.system_port = system.membus.slave 67 if options.arch == "mixed": 68 for i in xrange(int(options.num_tgen/2)): 69 system.tgen[i].port = system.membus.slave 70 hh = system.hmc_host 71 if options.enable_global_monitor: 72 system.tgen[2].port = hh.lmonitor[2].slave 73 hh.lmonitor[2].master = hh.seriallink[2].slave 74 system.tgen[3].port = hh.lmonitor[3].slave 75 hh.lmonitor[3].master = hh.seriallink[3].slave 76 else: 77 system.tgen[2].port = hh.seriallink[2].slave 78 system.tgen[3].port = hh.seriallink[3].slave 79 # connect the system port even if it is not used in this example 80 system.system_port = system.membus.slave 81 if options.arch == "same": 82 hh = system.hmc_host 83 for i in xrange(options.num_links_controllers): 84 if options.enable_global_monitor: 85 system.tgen[i].port = hh.lmonitor[i].slave 86 else: 87 system.tgen[i].port = hh.seriallink[i].slave 88 # set up the root SimObject 89 root = Root(full_system=False, system=system) 90 return root
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87
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88# determine the burst length in bytes 89burst_size = 256 90num_serial_links = 4 91num_vault_ctrl = 16 92options.mem_channels = 1 93options.external_memory_system = 0 94options.mem_ranks=1 95stride_size = burst_size 96system.cache_line_size = burst_size
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97
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98# Enable performance monitoring 99options.enable_global_monitor = True 100options.enable_link_monitor = False
| 93def main(): 94 parser = argparse.ArgumentParser(description="Simple system using HMC as\ 95 main memory") 96 HMC.add_options(parser) 97 add_options(parser) 98 options = parser.parse_args() 99 # build the system 100 root = build_system(options) 101 # instantiate all of the objects we've created so far 102 m5.instantiate() 103 print "Beginning simulation!" 104 event = m5.simulate(10000000000) 105 m5.stats.dump() 106 print 'Exiting @ tick %i because %s (exit code is %i)' % (m5.curTick(), 107 event.getCause(), 108 event.getCode()) 109 print "Done"
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101
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102# Bytes used for calculations 103oneGBytes = 1024 * 1024 * 1024 104oneMBytes = 1024 * 1024
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105
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106# Memory ranges of 16 vault controller - Total_HMC_size / 16 107mem_range_vault = [ AddrRange(i * 256 * oneMBytes, ((i + 1) * 256 * oneMBytes) 108 - 1) 109 for i in range(num_vault_ctrl)] 110 111# Memmory ranges of serial link for arch-0 112# Same as the ranges of vault controllers - 4 vault - to - 1 serial link 113if options.arch == "same": 114 ser_range = [ AddrRange(0, (4 * oneGBytes) - 1) 115 for i in range(num_serial_links)] 116 options.ser_ranges = ser_range 117 118# Memmory ranges of serial link for arch-1 119# Distributed range accross links 120if options.arch == "distributed": 121 ser_range = [ AddrRange(i * oneGBytes, ((i + 1) * oneGBytes) - 1) 122 for i in range(num_serial_links)] 123 options.ser_ranges = ser_range 124 125# Memmory ranges of serial link for arch-2 126# "Mixed" address distribution over links 127if options.arch == "mixed": 128 ser_range0 = AddrRange(0 , (1 * oneGBytes) - 1) 129 ser_range1 = AddrRange(1 * oneGBytes , (2 * oneGBytes) - 1) 130 ser_range2 = AddrRange(0 , (4 * oneGBytes) - 1) 131 ser_range3 = AddrRange(0 , (4 * oneGBytes) - 1) 132 options.ser_ranges = [ser_range0, ser_range1, ser_range2, ser_range3] 133 134# Assign ranges of vault controller to system ranges 135system.mem_ranges = mem_range_vault 136 137# open traffic generator 138cfg_file_name = "./tests/quick/se/70.tgen/traffic.cfg" 139cfg_file = open(cfg_file_name, 'r') 140 141# number of traffic generator 142np = 4 143# create a traffic generator, and point it to the file we just created 144system.tgen = [ TrafficGen(config_file = cfg_file_name) for i in xrange(np)] 145 146# Config memory system with given HMC arch 147MemConfig.config_mem(options, system) 148 149if options.arch == "distributed": 150 for i in xrange(np): 151 system.tgen[i].port = system.membus.slave 152 # connect the system port even if it is not used in this example 153 system.system_port = system.membus.slave 154 155if options.arch == "mixed": 156 for i in xrange(int(np/2)): 157 system.tgen[i].port = system.membus.slave 158 # connect the system port even if it is not used in this example 159 system.system_port = system.membus.slave 160 161 162# run Forrest, run! 163root = Root(full_system = False, system = system) 164root.system.mem_mode = 'timing' 165 166m5.instantiate() 167m5.simulate(10000000000) 168 169m5.stats.dump() 170 171print "Done!"
| 112if __name__ == "__m5_main__": 113 main()
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