1from __future__ import print_function 2 3import sys 4import argparse 5import subprocess 6from pprint import pprint 7 8import m5 --- 43 unchanged lines hidden (view full) --- 52 # use timing mode for the interaction between master-slave ports 53 system.mem_mode = 'timing' 54 # set the clock fequency of the system 55 clk = '100GHz' 56 vd = VoltageDomain(voltage='1V') 57 system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd) 58 # add traffic generators to the system 59 system.tgen = [TrafficGen(config_file=options.tgen_cfg_file) for i in |
60 range(options.num_tgen)] |
61 # Config memory system with given HMC arch 62 MemConfig.config_mem(options, system) 63 # Connect the traffic generatiors 64 if options.arch == "distributed": |
65 for i in range(options.num_tgen): |
66 system.tgen[i].port = system.membus.slave 67 # connect the system port even if it is not used in this example 68 system.system_port = system.membus.slave 69 if options.arch == "mixed": |
70 for i in range(int(options.num_tgen/2)): |
71 system.tgen[i].port = system.membus.slave 72 hh = system.hmc_host 73 if options.enable_global_monitor: 74 system.tgen[2].port = hh.lmonitor[2].slave 75 hh.lmonitor[2].master = hh.seriallink[2].slave 76 system.tgen[3].port = hh.lmonitor[3].slave 77 hh.lmonitor[3].master = hh.seriallink[3].slave 78 else: 79 system.tgen[2].port = hh.seriallink[2].slave 80 system.tgen[3].port = hh.seriallink[3].slave 81 # connect the system port even if it is not used in this example 82 system.system_port = system.membus.slave 83 if options.arch == "same": 84 hh = system.hmc_host |
85 for i in range(options.num_links_controllers): |
86 if options.enable_global_monitor: 87 system.tgen[i].port = hh.lmonitor[i].slave 88 else: 89 system.tgen[i].port = hh.seriallink[i].slave 90 # set up the root SimObject 91 root = Root(full_system=False, system=system) 92 return root 93 --- 22 unchanged lines hidden --- |