| etrace_replay.py (12014:f973caaf935d) | etrace_replay.py (12430:11cb907bd81b) |
|---|---|
| 1# Copyright (c) 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 90 unchanged lines hidden (view full) --- 99 voltage_domain = 100 system.cpu_voltage_domain) 101 102# All cpus belong to a common cpu_clk_domain, therefore running at a common 103# frequency. 104for cpu in system.cpu: 105 cpu.clk_domain = system.cpu_clk_domain 106 | 1# Copyright (c) 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 90 unchanged lines hidden (view full) --- 99 voltage_domain = 100 system.cpu_voltage_domain) 101 102# All cpus belong to a common cpu_clk_domain, therefore running at a common 103# frequency. 104for cpu in system.cpu: 105 cpu.clk_domain = system.cpu_clk_domain 106 |
| 107# BaseCPU no longer has default values for the BaseCPU.isa 108# createThreads() is needed to fill in the cpu.isa 109for cpu in system.cpu: 110 cpu.createThreads() 111 |
|
| 107# Assign input trace files to the Trace CPU 108system.cpu.instTraceFile=options.inst_trace_file 109system.cpu.dataTraceFile=options.data_trace_file 110 111# Configure the classic memory system options 112MemClass = Simulation.setMemClass(options) 113system.membus = SystemXBar() 114system.system_port = system.membus.slave 115CacheConfig.config_cache(options, system) 116MemConfig.config_mem(options, system) 117 118root = Root(full_system = False, system = system) 119Simulation.run(options, root, system, FutureClass) | 112# Assign input trace files to the Trace CPU 113system.cpu.instTraceFile=options.inst_trace_file 114system.cpu.dataTraceFile=options.data_trace_file 115 116# Configure the classic memory system options 117MemClass = Simulation.setMemClass(options) 118system.membus = SystemXBar() 119system.system_port = system.membus.slave 120CacheConfig.config_cache(options, system) 121MemConfig.config_mem(options, system) 122 123root = Root(full_system = False, system = system) 124Simulation.run(options, root, system, FutureClass) |