sweep.py (10832:33f1c7b65a88) sweep.py (10833:a4a2ba97a654)
1# Copyright (c) 2014-2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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88system.clk_domain = SrcClockDomain(clock = '1.5GHz',
89 voltage_domain =
90 VoltageDomain(voltage = '1V'))
91
92# we are fine with 256 MB memory for now
93mem_range = AddrRange('256MB')
94system.mem_ranges = [mem_range]
95
1# Copyright (c) 2014-2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 79 unchanged lines hidden (view full) ---

88system.clk_domain = SrcClockDomain(clock = '1.5GHz',
89 voltage_domain =
90 VoltageDomain(voltage = '1V'))
91
92# we are fine with 256 MB memory for now
93mem_range = AddrRange('256MB')
94system.mem_ranges = [mem_range]
95
96# do not worry about reserving space for the backing store
97mmap_using_noreserve = True
98
96# force a single channel to match the assumptions in the DRAM traffic
97# generator
98options.mem_channels = 1
99options.external_memory_system = 0
100MemConfig.config_mem(options, system)
101
102# the following assumes that we are using the native DRAM
103# controller, check to be sure
104if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
105 fatal("This script assumes the memory is a DRAMCtrl subclass")
106
99# force a single channel to match the assumptions in the DRAM traffic
100# generator
101options.mem_channels = 1
102options.external_memory_system = 0
103MemConfig.config_mem(options, system)
104
105# the following assumes that we are using the native DRAM
106# controller, check to be sure
107if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
108 fatal("This script assumes the memory is a DRAMCtrl subclass")
109
110# there is no point slowing things down by saving any data
111system.mem_ctrls[0].null = True
112
107# Set the address mapping based on input argument
108# Default to RoRaBaCoCh
109if options.addr_map == 0:
110 system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
111elif options.addr_map == 1:
112 system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
113else:
114 fatal("Did not specify a valid address map argument")

--- 86 unchanged lines hidden --- 		113# Set the address mapping based on input argument
114# Default to RoRaBaCoCh
115if options.addr_map == 0:
116 system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
117elif options.addr_map == 1:
118 system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
119else:
120 fatal("Did not specify a valid address map argument")

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