sweep.py (10392:0100f00a229e) | sweep.py (10405:7a618c07e663) |
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1# Copyright (c) 2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 68 unchanged lines hidden (view full) --- 77if args: 78 print "Error: script doesn't take any positional arguments" 79 sys.exit(1) 80 81# at the moment we stay with the default open-adaptive page policy, 82# and address mapping 83 84# start with the system itself, using a multi-layer 1.5 GHz | 1# Copyright (c) 2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 68 unchanged lines hidden (view full) --- 77if args: 78 print "Error: script doesn't take any positional arguments" 79 sys.exit(1) 80 81# at the moment we stay with the default open-adaptive page policy, 82# and address mapping 83 84# start with the system itself, using a multi-layer 1.5 GHz |
85# bus/crossbar, delivering 64 bytes / 5 cycles (one header cycle) | 85# crossbar, delivering 64 bytes / 5 cycles (one header cycle) |
86# which amounts to 19.2 GByte/s per layer and thus per port | 86# which amounts to 19.2 GByte/s per layer and thus per port |
87system = System(membus = NoncoherentBus(width = 16)) | 87system = System(membus = NoncoherentXBar(width = 16)) |
88system.clk_domain = SrcClockDomain(clock = '1.5GHz', 89 voltage_domain = 90 VoltageDomain(voltage = '1V')) 91 92# we are fine with 256 MB memory for now 93mem_range = AddrRange('256MB') 94system.mem_ranges = [mem_range] 95 --- 107 unchanged lines hidden --- | 88system.clk_domain = SrcClockDomain(clock = '1.5GHz', 89 voltage_domain = 90 VoltageDomain(voltage = '1V')) 91 92# we are fine with 256 MB memory for now 93mem_range = AddrRange('256MB') 94system.mem_ranges = [mem_range] 95 --- 107 unchanged lines hidden --- |