| sweep.py (10219:4161cfba9658) | sweep.py (10323:5169ebd26163) |
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| 1# Copyright (c) 2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 110 unchanged lines hidden (view full) --- 119 120# match the maximum bandwidth of the memory, the parameter is in ns 121# and we need it in ticks 122itt = system.mem_ctrls[0].tBURST.value * 1000000000000 123 124# assume we start at 0 125max_addr = mem_range.end 126 | 1# Copyright (c) 2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 110 unchanged lines hidden (view full) --- 119 120# match the maximum bandwidth of the memory, the parameter is in ns 121# and we need it in ticks 122itt = system.mem_ctrls[0].tBURST.value * 1000000000000 123 124# assume we start at 0 125max_addr = mem_range.end 126 |
| 127# use min of the page size and 512 bytes as that should be more than 128# enough 129max_stride = min(512, page_size) 130 |
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| 127# now we create the state by iterating over the stride size from burst | 131# now we create the state by iterating over the stride size from burst |
| 128# size to min of the page size and 1 kB, and from using only a single 129# bank up to the number of banks available | 132# size to the max stride, and from using only a single bank up to the 133# number of banks available |
| 130nxt_state = 0 131for bank in range(1, nbr_banks + 1): | 134nxt_state = 0 135for bank in range(1, nbr_banks + 1): |
| 132 for stride_size in range(burst_size, min(1024, page_size) + 1, burst_size): | 136 for stride_size in range(burst_size, max_stride + 1, burst_size): |
| 133 cfg_file.write("STATE %d %d DRAM 100 0 %d " 134 "%d %d %d %d %d %d %d %d 1\n" % 135 (nxt_state, period, max_addr, burst_size, itt, itt, 0, 136 stride_size, page_size, nbr_banks, bank)) 137 nxt_state = nxt_state + 1 138 139cfg_file.write("INIT 0\n") 140 --- 22 unchanged lines hidden (view full) --- 163periodicStatDump(period) 164 165# run Forrest, run! 166root = Root(full_system = False, system = system) 167root.system.mem_mode = 'timing' 168 169m5.instantiate() 170m5.simulate(nxt_state * period) | 137 cfg_file.write("STATE %d %d DRAM 100 0 %d " 138 "%d %d %d %d %d %d %d %d 1\n" % 139 (nxt_state, period, max_addr, burst_size, itt, itt, 0, 140 stride_size, page_size, nbr_banks, bank)) 141 nxt_state = nxt_state + 1 142 143cfg_file.write("INIT 0\n") 144 --- 22 unchanged lines hidden (view full) --- 167periodicStatDump(period) 168 169# run Forrest, run! 170root = Root(full_system = False, system = system) 171root.system.mem_mode = 'timing' 172 173m5.instantiate() 174m5.simulate(nxt_state * period) |
| 175 176print "DRAM sweep with burst: %d, banks: %d, max stride: %d" % \ 177 (burst_size, nbr_banks, max_stride) |
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