| sweep.py (10146:27dfed4c8403) | sweep.py (10219:4161cfba9658) |
|---|---|
| 1# Copyright (c) 2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 53 unchanged lines hidden (view full) --- 62 63if args: 64 print "Error: script doesn't take any positional arguments" 65 sys.exit(1) 66 67# at the moment we stay with the default open-adaptive page policy, 68# and address mapping 69 | 1# Copyright (c) 2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 53 unchanged lines hidden (view full) --- 62 63if args: 64 print "Error: script doesn't take any positional arguments" 65 sys.exit(1) 66 67# at the moment we stay with the default open-adaptive page policy, 68# and address mapping 69 |
| 70# start with the system itself, using a multi-layer 1 GHz | 70# start with the system itself, using a multi-layer 1.5 GHz |
| 71# bus/crossbar, delivering 64 bytes / 5 cycles (one header cycle) | 71# bus/crossbar, delivering 64 bytes / 5 cycles (one header cycle) |
| 72# which amounts to 12.8 GByte/s per layer and thus per port | 72# which amounts to 19.2 GByte/s per layer and thus per port |
| 73system = System(membus = NoncoherentBus(width = 16)) | 73system = System(membus = NoncoherentBus(width = 16)) |
| 74system.clk_domain = SrcClockDomain(clock = '1GHz', | 74system.clk_domain = SrcClockDomain(clock = '1.5GHz', |
| 75 voltage_domain = 76 VoltageDomain(voltage = '1V')) 77 78# we are fine with 256 MB memory for now 79mem_range = AddrRange('256MB') 80system.mem_ranges = [mem_range] 81 82# force a single channel to match the assumptions in the DRAM traffic --- 88 unchanged lines hidden --- | 75 voltage_domain = 76 VoltageDomain(voltage = '1V')) 77 78# we are fine with 256 MB memory for now 79mem_range = AddrRange('256MB') 80system.mem_ranges = [mem_range] 81 82# force a single channel to match the assumptions in the DRAM traffic --- 88 unchanged lines hidden --- |