1# Copyright (c) 2014-2015, 2018 ARM Limited |
2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 22 unchanged lines hidden (view full) --- 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37 38from __future__ import print_function 39 |
40import math |
41import optparse 42 43import m5 44from m5.objects import * 45from m5.util import addToPath 46from m5.stats import periodicStatDump 47 48addToPath('../') 49 50from common import MemConfig 51 52# this script is helpful to sweep the efficiency of a specific memory 53# controller configuration, by varying the number of banks accessed, 54# and the sequential stride size (how many bytes per activate), and 55# observe what bus utilisation (bandwidth) is achieved 56 57parser = optparse.OptionParser() 58 |
59dram_generators = { 60 "DRAM" : lambda x: x.createDram, 61 "DRAM_ROTATE" : lambda x: x.createDramRot, 62} 63 |
64# Use a single-channel DDR3-1600 x64 (8x8 topology) by default 65parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", 66 choices=MemConfig.mem_names(), 67 help = "type of memory to use") 68 69parser.add_option("--mem-ranks", "-r", type="int", default=1, 70 help = "Number of ranks to iterate across") 71 72parser.add_option("--rd_perc", type="int", default=100, 73 help = "Percentage of read commands") 74 75parser.add_option("--mode", type="choice", default="DRAM", |
76 choices=dram_generators.keys(), |
77 help = "DRAM: Random traffic; \ 78 DRAM_ROTATE: Traffic rotating across banks and ranks") 79 80parser.add_option("--addr_map", type="int", default=1, 81 help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo") 82 83(options, args) = parser.parse_args() 84 --- 43 unchanged lines hidden (view full) --- 128 system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh" 129else: 130 fatal("Did not specify a valid address map argument") 131 132# stay in each state for 0.25 ms, long enough to warm things up, and 133# short enough to avoid hitting a refresh 134period = 250000000 135 |
136# stay in each state as long as the dump/reset period, use the entire 137# range, issue transactions of the right DRAM burst size, and match 138# the DRAM maximum bandwidth to ensure that it is saturated 139 140# get the number of banks 141nbr_banks = system.mem_ctrls[0].banks_per_rank.value 142 143# determine the burst length in bytes --- 11 unchanged lines hidden (view full) --- 155 156# assume we start at 0 157max_addr = mem_range.end 158 159# use min of the page size and 512 bytes as that should be more than 160# enough 161max_stride = min(512, page_size) 162 |
163# create a traffic generator, and point it to the file we just created |
164system.tgen = PyTrafficGen() |
165 166# add a communication monitor 167system.monitor = CommMonitor() 168 169# connect the traffic generator to the bus via a communication monitor 170system.tgen.port = system.monitor.slave 171system.monitor.master = system.membus.slave 172 173# connect the system port even if it is not used in this example 174system.system_port = system.membus.slave 175 176# every period, dump and reset all stats 177periodicStatDump(period) 178 179# run Forrest, run! 180root = Root(full_system = False, system = system) 181root.system.mem_mode = 'timing' 182 183m5.instantiate() |
184 |
185def trace(): 186 generator = dram_generators[options.mode](system.tgen) 187 for bank in range(1, nbr_banks + 1): 188 for stride_size in range(burst_size, max_stride + 1, burst_size): 189 num_seq_pkts = int(math.ceil(float(stride_size) / burst_size)) 190 yield generator(period, 191 0, max_addr, burst_size, int(itt), int(itt), 192 options.rd_perc, 0, 193 num_seq_pkts, page_size, nbr_banks, bank, 194 options.addr_map, options.mem_ranks) 195 yield system.tgen.createExit(0) 196 197system.tgen.start(trace()) 198 199m5.simulate() 200 |
201print("DRAM sweep with burst: %d, banks: %d, max stride: %d" % 202 (burst_size, nbr_banks, max_stride)) |