1# Copyright (c) 2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
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53
54parser = optparse.OptionParser()
55
56# Use a single-channel DDR3-1600 x64 by default
57parser.add_option("--mem-type", type="choice", default="ddr3_1600_x64",
58 choices=MemConfig.mem_names(),
59 help = "type of memory to use")
60
61(options, args) = parser.parse_args()
62
63if args:
64 print "Error: script doesn't take any positional arguments"
65 sys.exit(1)
66
67# at the moment we stay with the default open-adaptive page policy,
68# and address mapping
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84options.mem_channels = 1
85MemConfig.config_mem(options, system)
86
87# the following assumes that we are using the native DRAM
88# controller, check to be sure
89if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
90 fatal("This script assumes the memory is a DRAMCtrl subclass")
91
92# for now the generator assumes a single rank
93system.mem_ctrls[0].ranks_per_channel = 1
94
95# stay in each state for 0.25 ms, long enough to warm things up, and
96# short enough to avoid hitting a refresh
97period = 250000000
98
99# this is where we go off piste, and print the traffic generator
100# configuration that we will later use, crazy but it works
101cfg_file_name = "configs/dram/sweep.cfg"
102cfg_file = open(cfg_file_name, 'w')
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129max_stride = min(512, page_size)
130
131# now we create the state by iterating over the stride size from burst
132# size to the max stride, and from using only a single bank up to the
133# number of banks available
134nxt_state = 0
135for bank in range(1, nbr_banks + 1):
136 for stride_size in range(burst_size, max_stride + 1, burst_size):
137 cfg_file.write("STATE %d %d DRAM 100 0 %d "
138 "%d %d %d %d %d %d %d %d 1\n" %
139 (nxt_state, period, max_addr, burst_size, itt, itt, 0,
140 stride_size, page_size, nbr_banks, bank))
141 nxt_state = nxt_state + 1
142
143cfg_file.write("INIT 0\n")
144
145# go through the states one by one
146for state in range(1, nxt_state):
147 cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state))
148
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2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
--- 44 unchanged lines hidden (view full) ---
53
54parser = optparse.OptionParser()
55
56# Use a single-channel DDR3-1600 x64 by default
57parser.add_option("--mem-type", type="choice", default="ddr3_1600_x64",
58 choices=MemConfig.mem_names(),
59 help = "type of memory to use")
60
61(options, args) = parser.parse_args()
62
63if args:
64 print "Error: script doesn't take any positional arguments"
65 sys.exit(1)
66
67# at the moment we stay with the default open-adaptive page policy,
68# and address mapping
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84options.mem_channels = 1
85MemConfig.config_mem(options, system)
86
87# the following assumes that we are using the native DRAM
88# controller, check to be sure
89if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
90 fatal("This script assumes the memory is a DRAMCtrl subclass")
91
92# for now the generator assumes a single rank
93system.mem_ctrls[0].ranks_per_channel = 1
94
95# stay in each state for 0.25 ms, long enough to warm things up, and
96# short enough to avoid hitting a refresh
97period = 250000000
98
99# this is where we go off piste, and print the traffic generator
100# configuration that we will later use, crazy but it works
101cfg_file_name = "configs/dram/sweep.cfg"
102cfg_file = open(cfg_file_name, 'w')
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129max_stride = min(512, page_size)
130
131# now we create the state by iterating over the stride size from burst
132# size to the max stride, and from using only a single bank up to the
133# number of banks available
134nxt_state = 0
135for bank in range(1, nbr_banks + 1):
136 for stride_size in range(burst_size, max_stride + 1, burst_size):
137 cfg_file.write("STATE %d %d DRAM 100 0 %d "
138 "%d %d %d %d %d %d %d %d 1\n" %
139 (nxt_state, period, max_addr, burst_size, itt, itt, 0,
140 stride_size, page_size, nbr_banks, bank))
141 nxt_state = nxt_state + 1
142
143cfg_file.write("INIT 0\n")
144
145# go through the states one by one
146for state in range(1, nxt_state):
147 cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state))
148
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