| lat_mem_rd.py (11656:02a0c6b9c057) | lat_mem_rd.py (11682:612f75cf36a0) |
|---|---|
| 1# Copyright (c) 2015-2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 30 unchanged lines hidden (view full) --- 39import optparse 40import os 41 42import m5 43from m5.objects import * 44from m5.util import addToPath 45from m5.internal.stats import periodicStatDump 46 | 1# Copyright (c) 2015-2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 30 unchanged lines hidden (view full) --- 39import optparse 40import os 41 42import m5 43from m5.objects import * 44from m5.util import addToPath 45from m5.internal.stats import periodicStatDump 46 |
| 47addToPath('../common') 48import MemConfig | 47addToPath('../') 48from common import MemConfig |
| 49 50addToPath('../../util') 51import protolib 52 53# this script is helpful to observe the memory latency for various 54# levels in a cache hierarchy, and various cache and memory 55# configurations, in essence replicating the lmbench lat_mem_rd thrash 56# behaviour --- 196 unchanged lines hidden (view full) --- 253# add a communication monitor 254system.monitor = CommMonitor() 255 256# connect the traffic generator to the system 257system.tgen.port = system.monitor.slave 258 259# create the actual cache hierarchy, for now just go with something 260# basic to explore some of the options | 49 50addToPath('../../util') 51import protolib 52 53# this script is helpful to observe the memory latency for various 54# levels in a cache hierarchy, and various cache and memory 55# configurations, in essence replicating the lmbench lat_mem_rd thrash 56# behaviour --- 196 unchanged lines hidden (view full) --- 253# add a communication monitor 254system.monitor = CommMonitor() 255 256# connect the traffic generator to the system 257system.tgen.port = system.monitor.slave 258 259# create the actual cache hierarchy, for now just go with something 260# basic to explore some of the options |
| 261from Caches import * | 261from common.Caches import * |
| 262 263# a starting point for an L3 cache 264class L3Cache(Cache): 265 assoc = 16 266 hit_latency = 40 267 response_latency = 40 268 mshrs = 32 269 tgts_per_mshr = 12 --- 37 unchanged lines hidden --- | 262 263# a starting point for an L3 cache 264class L3Cache(Cache): 265 assoc = 16 266 hit_latency = 40 267 response_latency = 40 268 mshrs = 32 269 tgts_per_mshr = 12 --- 37 unchanged lines hidden --- |