1# Copyright (c) 2015-2016 ARM Limited |
2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 232 unchanged lines hidden (view full) --- 242for state in range(1, nxt_state): 243 cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state)) 244 245cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1)) 246 247cfg_file.close() 248 249# create a traffic generator, and point it to the file we just created |
250system.tgen = TrafficGen(config_file = cfg_file_name, 251 progress_check = '10s') |
252 253# add a communication monitor 254system.monitor = CommMonitor() 255 256# connect the traffic generator to the system 257system.tgen.port = system.monitor.slave 258 259# create the actual cache hierarchy, for now just go with something --- 47 unchanged lines hidden --- |