1# Copyright (c) 2012 The Regents of The University of Michigan
2# Copyright (c) 2016 Centre National de la Recherche Scientifique
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Ron Dreslinski
29# Anastasiia Butko
30# Louisa Bessad
31
32from m5.objects import *
33
34#-----------------------------------------------------------------------
35# ex5 LITTLE core (based on the ARM Cortex-A7)
36#-----------------------------------------------------------------------
37
38# Simple ALU Instructions have a latency of 3
39class ex5_LITTLE_Simple_Int(MinorDefaultIntFU):
40 opList = [ OpDesc(opClass='IntAlu', opLat=4) ]
41
42# Complex ALU instructions have a variable latencies
43class ex5_LITTLE_Complex_IntMul(MinorDefaultIntMulFU):
44 opList = [ OpDesc(opClass='IntMult', opLat=7) ]
45
46class ex5_LITTLE_Complex_IntDiv(MinorDefaultIntDivFU):
47 opList = [ OpDesc(opClass='IntDiv', opLat=9) ]
48
49# Floating point and SIMD instructions
50class ex5_LITTLE_FP(MinorDefaultFloatSimdFU):
51 opList = [ OpDesc(opClass='SimdAdd', opLat=6),
52 OpDesc(opClass='SimdAddAcc', opLat=4),
53 OpDesc(opClass='SimdAlu', opLat=4),
54 OpDesc(opClass='SimdCmp', opLat=1),
55 OpDesc(opClass='SimdCvt', opLat=3),
56 OpDesc(opClass='SimdMisc', opLat=3),
57 OpDesc(opClass='SimdMult',opLat=4),
58 OpDesc(opClass='SimdMultAcc',opLat=5),
59 OpDesc(opClass='SimdShift',opLat=3),
60 OpDesc(opClass='SimdShiftAcc', opLat=3),
61 OpDesc(opClass='SimdSqrt', opLat=9),
62 OpDesc(opClass='SimdFloatAdd',opLat=8),
63 OpDesc(opClass='SimdFloatAlu',opLat=6),
64 OpDesc(opClass='SimdFloatCmp', opLat=6),
65 OpDesc(opClass='SimdFloatCvt', opLat=6),
66 OpDesc(opClass='SimdFloatDiv', opLat=20, pipelined=False),
67 OpDesc(opClass='SimdFloatMisc', opLat=6),
68 OpDesc(opClass='SimdFloatMult', opLat=15),
69 OpDesc(opClass='SimdFloatMultAcc',opLat=6),
70 OpDesc(opClass='SimdFloatSqrt', opLat=17),
71 OpDesc(opClass='FloatAdd', opLat=8),
72 OpDesc(opClass='FloatCmp', opLat=6),
73 OpDesc(opClass='FloatCvt', opLat=6),
74 OpDesc(opClass='FloatDiv', opLat=15, pipelined=False),
75 OpDesc(opClass='FloatSqrt', opLat=33),
76 OpDesc(opClass='FloatMult', opLat=6) ]
77
78# Load/Store Units
79class ex5_LITTLE_MemFU(MinorDefaultMemFU):
80 opList = [ OpDesc(opClass='MemRead',opLat=1),
81 OpDesc(opClass='MemWrite',opLat=1) ]
82
83# Misc Unit
84class ex5_LITTLE_MiscFU(MinorDefaultMiscFU):
85 opList = [ OpDesc(opClass='IprAccess',opLat=1),
86 OpDesc(opClass='InstPrefetch',opLat=1) ]
87
88# Functional Units for this CPU
89class ex5_LITTLE_FUP(MinorFUPool):
90 funcUnits = [ex5_LITTLE_Simple_Int(), ex5_LITTLE_Simple_Int(),
91 ex5_LITTLE_Complex_IntMul(), ex5_LITTLE_Complex_IntDiv(),
92 ex5_LITTLE_FP(), ex5_LITTLE_MemFU(),
93 ex5_LITTLE_MiscFU()]
94
95class ex5_LITTLE(MinorCPU):
96 executeFuncUnits = ex5_LITTLE_FUP()
97
98class L1Cache(Cache):
99 tag_latency = 2
100 data_latency = 2
101 response_latency = 2
102 tgts_per_mshr = 8
103 # Consider the L2 a victim cache also for clean lines
104 writeback_clean = True
105
106class L1I(L1Cache):
107 mshrs = 2
108 size = '32kB'
109 assoc = 2
110 is_read_only = True
111 tgts_per_mshr = 20
112
113class L1D(L1Cache):
114 mshrs = 4
115 size = '32kB'
116 assoc = 4
117 write_buffers = 4
118
119# TLB Cache
120# Use a cache as a L2 TLB
121class WalkCache(Cache):
122 tag_latency = 2
123 data_latency = 2
124 response_latency = 2
125 mshrs = 6
126 tgts_per_mshr = 8
127 size = '1kB'
128 assoc = 2
129 write_buffers = 16
130 is_read_only = True
131 # Writeback clean lines as well
132 writeback_clean = True
133
134# L2 Cache
135class L2(Cache):
136 tag_latency = 9
137 data_latency = 9
138 response_latency = 9
139 mshrs = 8
140 tgts_per_mshr = 12
141 size = '512kB'
142 assoc = 8
143 write_buffers = 16
144 prefetch_on_access = True
145 clusivity = 'mostly_excl'
146 # Simple stride prefetcher
147 prefetcher = StridePrefetcher(degree=1, latency = 1)
| 1# Copyright (c) 2012 The Regents of The University of Michigan
2# Copyright (c) 2016 Centre National de la Recherche Scientifique
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Ron Dreslinski
29# Anastasiia Butko
30# Louisa Bessad
31
32from m5.objects import *
33
34#-----------------------------------------------------------------------
35# ex5 LITTLE core (based on the ARM Cortex-A7)
36#-----------------------------------------------------------------------
37
38# Simple ALU Instructions have a latency of 3
39class ex5_LITTLE_Simple_Int(MinorDefaultIntFU):
40 opList = [ OpDesc(opClass='IntAlu', opLat=4) ]
41
42# Complex ALU instructions have a variable latencies
43class ex5_LITTLE_Complex_IntMul(MinorDefaultIntMulFU):
44 opList = [ OpDesc(opClass='IntMult', opLat=7) ]
45
46class ex5_LITTLE_Complex_IntDiv(MinorDefaultIntDivFU):
47 opList = [ OpDesc(opClass='IntDiv', opLat=9) ]
48
49# Floating point and SIMD instructions
50class ex5_LITTLE_FP(MinorDefaultFloatSimdFU):
51 opList = [ OpDesc(opClass='SimdAdd', opLat=6),
52 OpDesc(opClass='SimdAddAcc', opLat=4),
53 OpDesc(opClass='SimdAlu', opLat=4),
54 OpDesc(opClass='SimdCmp', opLat=1),
55 OpDesc(opClass='SimdCvt', opLat=3),
56 OpDesc(opClass='SimdMisc', opLat=3),
57 OpDesc(opClass='SimdMult',opLat=4),
58 OpDesc(opClass='SimdMultAcc',opLat=5),
59 OpDesc(opClass='SimdShift',opLat=3),
60 OpDesc(opClass='SimdShiftAcc', opLat=3),
61 OpDesc(opClass='SimdSqrt', opLat=9),
62 OpDesc(opClass='SimdFloatAdd',opLat=8),
63 OpDesc(opClass='SimdFloatAlu',opLat=6),
64 OpDesc(opClass='SimdFloatCmp', opLat=6),
65 OpDesc(opClass='SimdFloatCvt', opLat=6),
66 OpDesc(opClass='SimdFloatDiv', opLat=20, pipelined=False),
67 OpDesc(opClass='SimdFloatMisc', opLat=6),
68 OpDesc(opClass='SimdFloatMult', opLat=15),
69 OpDesc(opClass='SimdFloatMultAcc',opLat=6),
70 OpDesc(opClass='SimdFloatSqrt', opLat=17),
71 OpDesc(opClass='FloatAdd', opLat=8),
72 OpDesc(opClass='FloatCmp', opLat=6),
73 OpDesc(opClass='FloatCvt', opLat=6),
74 OpDesc(opClass='FloatDiv', opLat=15, pipelined=False),
75 OpDesc(opClass='FloatSqrt', opLat=33),
76 OpDesc(opClass='FloatMult', opLat=6) ]
77
78# Load/Store Units
79class ex5_LITTLE_MemFU(MinorDefaultMemFU):
80 opList = [ OpDesc(opClass='MemRead',opLat=1),
81 OpDesc(opClass='MemWrite',opLat=1) ]
82
83# Misc Unit
84class ex5_LITTLE_MiscFU(MinorDefaultMiscFU):
85 opList = [ OpDesc(opClass='IprAccess',opLat=1),
86 OpDesc(opClass='InstPrefetch',opLat=1) ]
87
88# Functional Units for this CPU
89class ex5_LITTLE_FUP(MinorFUPool):
90 funcUnits = [ex5_LITTLE_Simple_Int(), ex5_LITTLE_Simple_Int(),
91 ex5_LITTLE_Complex_IntMul(), ex5_LITTLE_Complex_IntDiv(),
92 ex5_LITTLE_FP(), ex5_LITTLE_MemFU(),
93 ex5_LITTLE_MiscFU()]
94
95class ex5_LITTLE(MinorCPU):
96 executeFuncUnits = ex5_LITTLE_FUP()
97
98class L1Cache(Cache):
99 tag_latency = 2
100 data_latency = 2
101 response_latency = 2
102 tgts_per_mshr = 8
103 # Consider the L2 a victim cache also for clean lines
104 writeback_clean = True
105
106class L1I(L1Cache):
107 mshrs = 2
108 size = '32kB'
109 assoc = 2
110 is_read_only = True
111 tgts_per_mshr = 20
112
113class L1D(L1Cache):
114 mshrs = 4
115 size = '32kB'
116 assoc = 4
117 write_buffers = 4
118
119# TLB Cache
120# Use a cache as a L2 TLB
121class WalkCache(Cache):
122 tag_latency = 2
123 data_latency = 2
124 response_latency = 2
125 mshrs = 6
126 tgts_per_mshr = 8
127 size = '1kB'
128 assoc = 2
129 write_buffers = 16
130 is_read_only = True
131 # Writeback clean lines as well
132 writeback_clean = True
133
134# L2 Cache
135class L2(Cache):
136 tag_latency = 9
137 data_latency = 9
138 response_latency = 9
139 mshrs = 8
140 tgts_per_mshr = 12
141 size = '512kB'
142 assoc = 8
143 write_buffers = 16
144 prefetch_on_access = True
145 clusivity = 'mostly_excl'
146 # Simple stride prefetcher
147 prefetcher = StridePrefetcher(degree=1, latency = 1)
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