1# Copyright (c) 2012 The Regents of The University of Michigan
2# Copyright (c) 2016 Centre National de la Recherche Scientifique
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Ron Dreslinski
29# Anastasiia Butko
30# Louisa Bessad
31
32from __future__ import print_function
33from __future__ import absolute_import
34
35from m5.objects import *
36
37#-----------------------------------------------------------------------
38# ex5 LITTLE core (based on the ARM Cortex-A7)
39#-----------------------------------------------------------------------
40
41# Simple ALU Instructions have a latency of 3
42class ex5_LITTLE_Simple_Int(MinorDefaultIntFU):
43 opList = [ OpDesc(opClass='IntAlu', opLat=4) ]
44
45# Complex ALU instructions have a variable latencies
46class ex5_LITTLE_Complex_IntMul(MinorDefaultIntMulFU):
47 opList = [ OpDesc(opClass='IntMult', opLat=7) ]
48
49class ex5_LITTLE_Complex_IntDiv(MinorDefaultIntDivFU):
50 opList = [ OpDesc(opClass='IntDiv', opLat=9) ]
51
52# Floating point and SIMD instructions
53class ex5_LITTLE_FP(MinorDefaultFloatSimdFU):
54 opList = [ OpDesc(opClass='SimdAdd', opLat=6),
55 OpDesc(opClass='SimdAddAcc', opLat=4),
56 OpDesc(opClass='SimdAlu', opLat=4),
57 OpDesc(opClass='SimdCmp', opLat=1),
58 OpDesc(opClass='SimdCvt', opLat=3),
59 OpDesc(opClass='SimdMisc', opLat=3),
60 OpDesc(opClass='SimdMult',opLat=4),
61 OpDesc(opClass='SimdMultAcc',opLat=5),
62 OpDesc(opClass='SimdShift',opLat=3),
63 OpDesc(opClass='SimdShiftAcc', opLat=3),
64 OpDesc(opClass='SimdSqrt', opLat=9),
65 OpDesc(opClass='SimdFloatAdd',opLat=8),
66 OpDesc(opClass='SimdFloatAlu',opLat=6),
67 OpDesc(opClass='SimdFloatCmp', opLat=6),
68 OpDesc(opClass='SimdFloatCvt', opLat=6),
69 OpDesc(opClass='SimdFloatDiv', opLat=20, pipelined=False),
70 OpDesc(opClass='SimdFloatMisc', opLat=6),
71 OpDesc(opClass='SimdFloatMult', opLat=15),
72 OpDesc(opClass='SimdFloatMultAcc',opLat=6),
73 OpDesc(opClass='SimdFloatSqrt', opLat=17),
74 OpDesc(opClass='FloatAdd', opLat=8),
75 OpDesc(opClass='FloatCmp', opLat=6),
76 OpDesc(opClass='FloatCvt', opLat=6),
77 OpDesc(opClass='FloatDiv', opLat=15, pipelined=False),
78 OpDesc(opClass='FloatSqrt', opLat=33),
79 OpDesc(opClass='FloatMult', opLat=6) ]
80
81# Load/Store Units
82class ex5_LITTLE_MemFU(MinorDefaultMemFU):
83 opList = [ OpDesc(opClass='MemRead',opLat=1),
84 OpDesc(opClass='MemWrite',opLat=1) ]
85
86# Misc Unit
87class ex5_LITTLE_MiscFU(MinorDefaultMiscFU):
88 opList = [ OpDesc(opClass='IprAccess',opLat=1),
89 OpDesc(opClass='InstPrefetch',opLat=1) ]
90
91# Functional Units for this CPU
92class ex5_LITTLE_FUP(MinorFUPool):
93 funcUnits = [ex5_LITTLE_Simple_Int(), ex5_LITTLE_Simple_Int(),
94 ex5_LITTLE_Complex_IntMul(), ex5_LITTLE_Complex_IntDiv(),
95 ex5_LITTLE_FP(), ex5_LITTLE_MemFU(),
96 ex5_LITTLE_MiscFU()]
97
98class ex5_LITTLE(MinorCPU):
99 executeFuncUnits = ex5_LITTLE_FUP()
100
101class L1Cache(Cache):
102 tag_latency = 2
103 data_latency = 2
104 response_latency = 2
105 tgts_per_mshr = 8
106 # Consider the L2 a victim cache also for clean lines
107 writeback_clean = True
108
109class L1I(L1Cache):
110 mshrs = 2
111 size = '32kB'
112 assoc = 2
113 is_read_only = True
114 tgts_per_mshr = 20
115
116class L1D(L1Cache):
117 mshrs = 4
118 size = '32kB'
119 assoc = 4
120 write_buffers = 4
121
122# TLB Cache
123# Use a cache as a L2 TLB
124class WalkCache(Cache):
125 tag_latency = 2
126 data_latency = 2
127 response_latency = 2
128 mshrs = 6
129 tgts_per_mshr = 8
130 size = '1kB'
131 assoc = 2
132 write_buffers = 16
133 is_read_only = True
134 # Writeback clean lines as well
135 writeback_clean = True
136
137# L2 Cache
138class L2(Cache):
139 tag_latency = 9
140 data_latency = 9
141 response_latency = 9
142 mshrs = 8
143 tgts_per_mshr = 12
144 size = '512kB'
145 assoc = 8
146 write_buffers = 16
147 prefetch_on_access = True
148 clusivity = 'mostly_excl'
149 # Simple stride prefetcher
150 prefetcher = StridePrefetcher(degree=1, latency = 1)
151 tags = BaseSetAssoc()
152 replacement_policy = RandomRP()