1# Copyright (c) 2012 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29
30from m5.objects import *
31
32# Simple ALU Instructions have a latency of 1
33class O3_ARM_v7a_Simple_Int(FUDesc):
34 opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
35 count = 2
36
37# Complex ALU instructions have a variable latencies
38class O3_ARM_v7a_Complex_Int(FUDesc):
39 opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True),
40 OpDesc(opClass='IntDiv', opLat=12, pipelined=False),
41 OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
42 count = 1
43
44
45# Floating point and SIMD instructions
46class O3_ARM_v7a_FP(FUDesc):
47 opList = [ OpDesc(opClass='SimdAdd', opLat=4),
48 OpDesc(opClass='SimdAddAcc', opLat=4),
49 OpDesc(opClass='SimdAlu', opLat=4),
50 OpDesc(opClass='SimdCmp', opLat=4),
51 OpDesc(opClass='SimdCvt', opLat=3),
52 OpDesc(opClass='SimdMisc', opLat=3),
53 OpDesc(opClass='SimdMult',opLat=5),
54 OpDesc(opClass='SimdMultAcc',opLat=5),
55 OpDesc(opClass='SimdShift',opLat=3),
56 OpDesc(opClass='SimdShiftAcc', opLat=3),
57 OpDesc(opClass='SimdSqrt', opLat=9),
58 OpDesc(opClass='SimdFloatAdd',opLat=5),
59 OpDesc(opClass='SimdFloatAlu',opLat=5),
60 OpDesc(opClass='SimdFloatCmp', opLat=3),
61 OpDesc(opClass='SimdFloatCvt', opLat=3),
62 OpDesc(opClass='SimdFloatDiv', opLat=3),
63 OpDesc(opClass='SimdFloatMisc', opLat=3),
64 OpDesc(opClass='SimdFloatMult', opLat=3),
65 OpDesc(opClass='SimdFloatMultAcc',opLat=5),
66 OpDesc(opClass='SimdFloatSqrt', opLat=9),
67 OpDesc(opClass='FloatAdd', opLat=5),
68 OpDesc(opClass='FloatCmp', opLat=5),
69 OpDesc(opClass='FloatCvt', opLat=5),
70 OpDesc(opClass='FloatDiv', opLat=9, pipelined=False),
71 OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
72 OpDesc(opClass='FloatMult', opLat=4),
73 OpDesc(opClass='FloatMultAcc', opLat=5),
74 OpDesc(opClass='FloatMisc', opLat=3) ]
75 count = 2
76
77
78# Load/Store Units
79class O3_ARM_v7a_Load(FUDesc):
80 opList = [ OpDesc(opClass='MemRead',opLat=2),
81 OpDesc(opClass='FloatMemRead',opLat=2) ]
82 count = 1
83
84class O3_ARM_v7a_Store(FUDesc):
85 opList = [ OpDesc(opClass='MemWrite',opLat=2),
86 OpDesc(opClass='FloatMemWrite',opLat=2) ]
87 count = 1
88
89# Functional Units for this CPU
90class O3_ARM_v7a_FUP(FUPool):
91 FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(),
92 O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()]
93
94# Bi-Mode Branch Predictor
95class O3_ARM_v7a_BP(BiModeBP):
96 globalPredictorSize = 8192
97 globalCtrBits = 2
98 choicePredictorSize = 8192
99 choiceCtrBits = 2
100 BTBEntries = 2048
101 BTBTagSize = 18
102 RASSize = 16
103 instShiftAmt = 2
104
105class O3_ARM_v7a_3(DerivO3CPU):
106 LQEntries = 16
107 SQEntries = 16
108 LSQDepCheckShift = 0
109 LFSTSize = 1024
110 SSITSize = 1024
111 decodeToFetchDelay = 1
112 renameToFetchDelay = 1
113 iewToFetchDelay = 1
114 commitToFetchDelay = 1
115 renameToDecodeDelay = 1
116 iewToDecodeDelay = 1
117 commitToDecodeDelay = 1
118 iewToRenameDelay = 1
119 commitToRenameDelay = 1
120 commitToIEWDelay = 1
121 fetchWidth = 3
122 fetchBufferSize = 16
123 fetchToDecodeDelay = 3
124 decodeWidth = 3
125 decodeToRenameDelay = 2
126 renameWidth = 3
127 renameToIEWDelay = 1
128 issueToExecuteDelay = 1
129 dispatchWidth = 6
130 issueWidth = 8
131 wbWidth = 8
132 fuPool = O3_ARM_v7a_FUP()
133 iewToCommitDelay = 1
134 renameToROBDelay = 1
135 commitWidth = 8
136 squashWidth = 8
137 trapLatency = 13
138 backComSize = 5
139 forwardComSize = 5
140 numPhysIntRegs = 128
141 numPhysFloatRegs = 192
| 1# Copyright (c) 2012 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29
30from m5.objects import *
31
32# Simple ALU Instructions have a latency of 1
33class O3_ARM_v7a_Simple_Int(FUDesc):
34 opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
35 count = 2
36
37# Complex ALU instructions have a variable latencies
38class O3_ARM_v7a_Complex_Int(FUDesc):
39 opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True),
40 OpDesc(opClass='IntDiv', opLat=12, pipelined=False),
41 OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
42 count = 1
43
44
45# Floating point and SIMD instructions
46class O3_ARM_v7a_FP(FUDesc):
47 opList = [ OpDesc(opClass='SimdAdd', opLat=4),
48 OpDesc(opClass='SimdAddAcc', opLat=4),
49 OpDesc(opClass='SimdAlu', opLat=4),
50 OpDesc(opClass='SimdCmp', opLat=4),
51 OpDesc(opClass='SimdCvt', opLat=3),
52 OpDesc(opClass='SimdMisc', opLat=3),
53 OpDesc(opClass='SimdMult',opLat=5),
54 OpDesc(opClass='SimdMultAcc',opLat=5),
55 OpDesc(opClass='SimdShift',opLat=3),
56 OpDesc(opClass='SimdShiftAcc', opLat=3),
57 OpDesc(opClass='SimdSqrt', opLat=9),
58 OpDesc(opClass='SimdFloatAdd',opLat=5),
59 OpDesc(opClass='SimdFloatAlu',opLat=5),
60 OpDesc(opClass='SimdFloatCmp', opLat=3),
61 OpDesc(opClass='SimdFloatCvt', opLat=3),
62 OpDesc(opClass='SimdFloatDiv', opLat=3),
63 OpDesc(opClass='SimdFloatMisc', opLat=3),
64 OpDesc(opClass='SimdFloatMult', opLat=3),
65 OpDesc(opClass='SimdFloatMultAcc',opLat=5),
66 OpDesc(opClass='SimdFloatSqrt', opLat=9),
67 OpDesc(opClass='FloatAdd', opLat=5),
68 OpDesc(opClass='FloatCmp', opLat=5),
69 OpDesc(opClass='FloatCvt', opLat=5),
70 OpDesc(opClass='FloatDiv', opLat=9, pipelined=False),
71 OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
72 OpDesc(opClass='FloatMult', opLat=4),
73 OpDesc(opClass='FloatMultAcc', opLat=5),
74 OpDesc(opClass='FloatMisc', opLat=3) ]
75 count = 2
76
77
78# Load/Store Units
79class O3_ARM_v7a_Load(FUDesc):
80 opList = [ OpDesc(opClass='MemRead',opLat=2),
81 OpDesc(opClass='FloatMemRead',opLat=2) ]
82 count = 1
83
84class O3_ARM_v7a_Store(FUDesc):
85 opList = [ OpDesc(opClass='MemWrite',opLat=2),
86 OpDesc(opClass='FloatMemWrite',opLat=2) ]
87 count = 1
88
89# Functional Units for this CPU
90class O3_ARM_v7a_FUP(FUPool):
91 FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(),
92 O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()]
93
94# Bi-Mode Branch Predictor
95class O3_ARM_v7a_BP(BiModeBP):
96 globalPredictorSize = 8192
97 globalCtrBits = 2
98 choicePredictorSize = 8192
99 choiceCtrBits = 2
100 BTBEntries = 2048
101 BTBTagSize = 18
102 RASSize = 16
103 instShiftAmt = 2
104
105class O3_ARM_v7a_3(DerivO3CPU):
106 LQEntries = 16
107 SQEntries = 16
108 LSQDepCheckShift = 0
109 LFSTSize = 1024
110 SSITSize = 1024
111 decodeToFetchDelay = 1
112 renameToFetchDelay = 1
113 iewToFetchDelay = 1
114 commitToFetchDelay = 1
115 renameToDecodeDelay = 1
116 iewToDecodeDelay = 1
117 commitToDecodeDelay = 1
118 iewToRenameDelay = 1
119 commitToRenameDelay = 1
120 commitToIEWDelay = 1
121 fetchWidth = 3
122 fetchBufferSize = 16
123 fetchToDecodeDelay = 3
124 decodeWidth = 3
125 decodeToRenameDelay = 2
126 renameWidth = 3
127 renameToIEWDelay = 1
128 issueToExecuteDelay = 1
129 dispatchWidth = 6
130 issueWidth = 8
131 wbWidth = 8
132 fuPool = O3_ARM_v7a_FUP()
133 iewToCommitDelay = 1
134 renameToROBDelay = 1
135 commitWidth = 8
136 squashWidth = 8
137 trapLatency = 13
138 backComSize = 5
139 forwardComSize = 5
140 numPhysIntRegs = 128
141 numPhysFloatRegs = 192
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