Simulation.py (9494:50da272a1300) Simulation.py (9518:8faae62af8c3)
1# Copyright (c) 2012 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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59
60 Restoring from a checkpoint or fast forwarding through a benchmark
61 can be done using one type of cpu, and then the actual
62 simulation can be carried out using another type. This function
63 returns these two types of cpus and the initial mode of operation
64 depending on the options provided.
65 """
66
13# Copyright (c) 2006-2008 The Regents of The University of Michigan
14# Copyright (c) 2010 Advanced Micro Devices, Inc.
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;

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71
72 Restoring from a checkpoint or fast forwarding through a benchmark
73 can be done using one type of cpu, and then the actual
74 simulation can be carried out using another type. This function
75 returns these two types of cpus and the initial mode of operation
76 depending on the options provided.
77 """
78
67 if options.cpu_type == "detailed" or \
68 options.cpu_type == "arm_detailed" or \
69 options.cpu_type == "inorder" :
70 if not options.caches and not options.ruby:
71 fatal("O3/Inorder CPU must be used with caches")
72
73 TmpClass, test_mem_mode = getCPUClass(options.cpu_type)
74 CPUClass = None
79 TmpClass, test_mem_mode = getCPUClass(options.cpu_type)
80 CPUClass = None
81 if TmpClass.require_caches() and \
82 not options.caches and not options.ruby:
83 fatal("%s must be used with caches" % options.cpu_type)
75
76 if options.checkpoint_restore != None:
77 if options.restore_with_cpu != options.cpu_type:
78 CPUClass = TmpClass
79 TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu)
80 elif options.fast_forward:
81 CPUClass = TmpClass
82 TmpClass = AtomicSimpleCPU

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312 # Add checker cpu if selected
313 if options.checker:
314 switch_cpus[i].addCheckerCpu()
315
316 testsys.switch_cpus = switch_cpus
317 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
318
319 if options.repeat_switch:
84
85 if options.checkpoint_restore != None:
86 if options.restore_with_cpu != options.cpu_type:
87 CPUClass = TmpClass
88 TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu)
89 elif options.fast_forward:
90 CPUClass = TmpClass
91 TmpClass = AtomicSimpleCPU

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321 # Add checker cpu if selected
322 if options.checker:
323 switch_cpus[i].addCheckerCpu()
324
325 testsys.switch_cpus = switch_cpus
326 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
327
328 if options.repeat_switch:
320 if options.cpu_type == "arm_detailed":
321 if not options.caches:
322 print "O3 CPU must be used with caches"
323 sys.exit(1)
324
325 repeat_switch_cpus = [O3_ARM_v7a_3(switched_out=True, \
326 cpu_id=(i)) for i in xrange(np)]
327 elif options.cpu_type == "detailed":
328 if not options.caches:
329 print "O3 CPU must be used with caches"
330 sys.exit(1)
331
332 repeat_switch_cpus = [DerivO3CPU(switched_out=True, \
333 cpu_id=(i)) for i in xrange(np)]
334 elif options.cpu_type == "inorder":
335 print "inorder CPU switching not supported"
329 switch_class = getCPUClass(options.cpu_type)[0]
330 if switch_class.require_caches() and \
331 not options.caches:
332 print "%s: Must be used with caches" % str(switch_class)
336 sys.exit(1)
333 sys.exit(1)
337 elif options.cpu_type == "timing":
338 repeat_switch_cpus = [TimingSimpleCPU(switched_out=True, \
339 cpu_id=(i)) for i in xrange(np)]
340 else:
341 repeat_switch_cpus = [AtomicSimpleCPU(switched_out=True, \
342 cpu_id=(i)) for i in xrange(np)]
334 if not switch_class.support_take_over():
335 print "%s: CPU switching not supported" % str(switch_class)
336 sys.exit(1)
343
337
338 repeat_switch_cpus = [switch_class(switched_out=True, \
339 cpu_id=(i)) for i in xrange(np)]
340
344 for i in xrange(np):
345 repeat_switch_cpus[i].system = testsys
346 repeat_switch_cpus[i].workload = testsys.cpu[i].workload
347 repeat_switch_cpus[i].clock = testsys.cpu[i].clock
348
349 if options.maxinsts:
350 repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts
351

--- 160 unchanged lines hidden --- 		341 for i in xrange(np):
342 repeat_switch_cpus[i].system = testsys
343 repeat_switch_cpus[i].workload = testsys.cpu[i].workload
344 repeat_switch_cpus[i].clock = testsys.cpu[i].clock
345
346 if options.maxinsts:
347 repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts
348

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