Simulation.py (8718:062bf3879857) Simulation.py (8724:7b4d80b26e35)
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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29
30from os import getcwd
31from os.path import join as joinpath
32
33import m5
34from m5.defines import buildEnv
35from m5.objects import *
36from m5.util import *
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 20 unchanged lines hidden (view full) ---

29
30from os import getcwd
31from os.path import join as joinpath
32
33import m5
34from m5.defines import buildEnv
35from m5.objects import *
36from m5.util import *
37from O3_ARM_v7a import *
37
38addToPath('../common')
39
40def setCPUClass(options):
41
42 atomic = False
43 if options.cpu_type == "timing":
44 class TmpClass(TimingSimpleCPU): pass
38
39addToPath('../common')
40
41def setCPUClass(options):
42
43 atomic = False
44 if options.cpu_type == "timing":
45 class TmpClass(TimingSimpleCPU): pass
45 elif options.cpu_type == "detailed":
46 elif options.cpu_type == "detailed" or options.cpu_type == "arm_detailed":
46 if not options.caches and not options.ruby:
47 print "O3 CPU must be used with caches"
48 sys.exit(1)
47 if not options.caches and not options.ruby:
48 print "O3 CPU must be used with caches"
49 sys.exit(1)
49 class TmpClass(DerivO3CPU): pass
50 if options.cpu_type == "arm_detailed":
51 class TmpClass(O3_ARM_v7a_3): pass
52 else:
53 class TmpClass(DerivO3CPU): pass
50 elif options.cpu_type == "inorder":
51 if not options.caches:
52 print "InOrder CPU must be used with caches"
53 sys.exit(1)
54 class TmpClass(InOrderCPU): pass
55 else:
56 class TmpClass(AtomicSimpleCPU): pass
57 atomic = True

--- 325 unchanged lines hidden --- 		54 elif options.cpu_type == "inorder":
55 if not options.caches:
56 print "InOrder CPU must be used with caches"
57 sys.exit(1)
58 class TmpClass(InOrderCPU): pass
59 else:
60 class TmpClass(AtomicSimpleCPU): pass
61 atomic = True

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