Simulation.py (8689:ec5f79b99ac3) Simulation.py (8718:062bf3879857)
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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38addToPath('../common')
39
40def setCPUClass(options):
41
42 atomic = False
43 if options.cpu_type == "timing":
44 class TmpClass(TimingSimpleCPU): pass
45 elif options.cpu_type == "detailed":
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 29 unchanged lines hidden (view full) ---

38addToPath('../common')
39
40def setCPUClass(options):
41
42 atomic = False
43 if options.cpu_type == "timing":
44 class TmpClass(TimingSimpleCPU): pass
45 elif options.cpu_type == "detailed":
46 if not options.caches:
46 if not options.caches and not options.ruby:
47 print "O3 CPU must be used with caches"
48 sys.exit(1)
49 class TmpClass(DerivO3CPU): pass
50 elif options.cpu_type == "inorder":
51 if not options.caches:
52 print "InOrder CPU must be used with caches"
53 sys.exit(1)
54 class TmpClass(InOrderCPU): pass

--- 328 unchanged lines hidden --- 		47 print "O3 CPU must be used with caches"
48 sys.exit(1)
49 class TmpClass(DerivO3CPU): pass
50 elif options.cpu_type == "inorder":
51 if not options.caches:
52 print "InOrder CPU must be used with caches"
53 sys.exit(1)
54 class TmpClass(InOrderCPU): pass

--- 328 unchanged lines hidden ---