Simulation.py (7766:1252ec1c8714) Simulation.py (8211:5275c2fbe957)
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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118 # simulation period
119 if options.max_inst:
120 switch_cpus[i].max_insts_any_thread = options.max_inst
121
122 testsys.switch_cpus = switch_cpus
123 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
124
125 if options.standard_switch:
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 109 unchanged lines hidden (view full) ---

118 # simulation period
119 if options.max_inst:
120 switch_cpus[i].max_insts_any_thread = options.max_inst
121
122 testsys.switch_cpus = switch_cpus
123 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
124
125 if options.standard_switch:
126 if not options.caches:
127 # O3 CPU must have a cache to work.
128 print "O3 CPU must be used with caches"
129 sys.exit(1)
130
126 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
127 for i in xrange(np)]
128 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
129 for i in xrange(np)]
130
131 for i in xrange(np):
132 switch_cpus[i].system = testsys
133 switch_cpus_1[i].system = testsys

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156 # warmup period
157 if options.warmup_insts:
158 switch_cpus[i].max_insts_any_thread = options.warmup_insts
159
160 # simulation period
161 if options.max_inst:
162 switch_cpus_1[i].max_insts_any_thread = options.max_inst
163
131 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
132 for i in xrange(np)]
133 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
134 for i in xrange(np)]
135
136 for i in xrange(np):
137 switch_cpus[i].system = testsys
138 switch_cpus_1[i].system = testsys

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161 # warmup period
162 if options.warmup_insts:
163 switch_cpus[i].max_insts_any_thread = options.warmup_insts
164
165 # simulation period
166 if options.max_inst:
167 switch_cpus_1[i].max_insts_any_thread = options.max_inst
168
164 if not options.caches:
165 # O3 CPU must have a cache to work.
166 print "O3 CPU must be used with caches"
167 sys.exit(1)
169 testsys.switch_cpus = switch_cpus
170 testsys.switch_cpus_1 = switch_cpus_1
171 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
172 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
168
173
169 testsys.switch_cpus = switch_cpus
170 testsys.switch_cpus_1 = switch_cpus_1
171 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
172 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
173
174 # set the checkpoint in the cpu before m5.instantiate is called
175 if options.take_checkpoints != None and \
176 (options.simpoint or options.at_instruction):
177 offset = int(options.take_checkpoints)
178 # Set an instruction break point
179 if options.simpoint:
180 for i in xrange(np):
181 if testsys.cpu[i].workload[0].simpoint == 0:

--- 193 unchanged lines hidden --- 		174 # set the checkpoint in the cpu before m5.instantiate is called
175 if options.take_checkpoints != None and \
176 (options.simpoint or options.at_instruction):
177 offset = int(options.take_checkpoints)
178 # Set an instruction break point
179 if options.simpoint:
180 for i in xrange(np):
181 if testsys.cpu[i].workload[0].simpoint == 0:

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