Simulation.py (5869:acbe11bbfe68) Simulation.py (6107:52a5e1c63380)
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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26#
27# Authors: Lisa Hsu
28
29from os import getcwd
30from os.path import join as joinpath
31import m5
32from m5.objects import *
33m5.AddToPath('../common')
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 17 unchanged lines hidden (view full) ---

26#
27# Authors: Lisa Hsu
28
29from os import getcwd
30from os.path import join as joinpath
31import m5
32from m5.objects import *
33m5.AddToPath('../common')
34from Caches import L1Cache
35
36def setCPUClass(options):
37
38 atomic = False
39 if options.timing:
40 class TmpClass(TimingSimpleCPU): pass
41 elif options.detailed:
42 if not options.caches:

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146 switch_cpus[i].max_insts_any_thread = options.warmup_insts
147
148 # simulation period
149 if options.max_inst:
150 switch_cpus_1[i].max_insts_any_thread = options.max_inst
151
152 if not options.caches:
153 # O3 CPU must have a cache to work.
34
35def setCPUClass(options):
36
37 atomic = False
38 if options.timing:
39 class TmpClass(TimingSimpleCPU): pass
40 elif options.detailed:
41 if not options.caches:

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145 switch_cpus[i].max_insts_any_thread = options.warmup_insts
146
147 # simulation period
148 if options.max_inst:
149 switch_cpus_1[i].max_insts_any_thread = options.max_inst
150
151 if not options.caches:
152 # O3 CPU must have a cache to work.
154 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
155 L1Cache(size = '64kB'))
156 switch_cpus_1[i].connectMemPorts(testsys.membus)
153 print "O3 CPU must be used with caches"
154 sys.exit(1)
157
158 testsys.switch_cpus = switch_cpus
159 testsys.switch_cpus_1 = switch_cpus_1
160 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
161 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
162
163 # set the checkpoint in the cpu before m5.instantiate is called
164 if options.take_checkpoints != None and \

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156 testsys.switch_cpus = switch_cpus
157 testsys.switch_cpus_1 = switch_cpus_1
158 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
159 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
160
161 # set the checkpoint in the cpu before m5.instantiate is called
162 if options.take_checkpoints != None and \

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