Simulation.py (3631:cebd6af96efd) Simulation.py (3681:129a68314264)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 25 unchanged lines hidden (view full) ---

34from Caches import L1Cache
35
36def setCPUClass(options):
37
38 atomic = False
39 if options.timing:
40 TmpClass = TimingSimpleCPU
41 elif options.detailed:
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 25 unchanged lines hidden (view full) ---

34from Caches import L1Cache
35
36def setCPUClass(options):
37
38 atomic = False
39 if options.timing:
40 TmpClass = TimingSimpleCPU
41 elif options.detailed:
42 if not options.caches:
43 print "O3 CPU must be used with caches"
44 sys.exit(1)
42 TmpClass = DerivO3CPU
43 else:
44 TmpClass = AtomicSimpleCPU
45 atomic = True
46
47 CPUClass = None
48 test_mem_mode = 'atomic'
49

--- 166 unchanged lines hidden --- 		45 TmpClass = DerivO3CPU
46 else:
47 TmpClass = AtomicSimpleCPU
48 atomic = True
49
50 CPUClass = None
51 test_mem_mode = 'atomic'
52

--- 166 unchanged lines hidden ---