Simulation.py (3511:8cb26619b6ec) Simulation.py (3514:b166ee5dce91)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29from os import getcwd
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29from os import getcwd
30from os.path import join as joinpath
31import m5
32from m5.objects import *
33m5.AddToPath('../common')
34from Caches import L1Cache
35
36def setCPUClass(options):
37
38 atomic = False

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60def run(options, root, testsys, cpu_class):
61 if options.maxtick:
62 maxtick = options.maxtick
63 elif options.maxtime:
64 simtime = int(options.maxtime * root.clock.value)
65 print "simulating for: ", simtime
66 maxtick = simtime
67 else:
30import m5
31from m5.objects import *
32m5.AddToPath('../common')
33from Caches import L1Cache
34
35def setCPUClass(options):
36
37 atomic = False

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59def run(options, root, testsys, cpu_class):
60 if options.maxtick:
61 maxtick = options.maxtick
62 elif options.maxtime:
63 simtime = int(options.maxtime * root.clock.value)
64 print "simulating for: ", simtime
65 maxtick = simtime
66 else:
68 maxtick = m5.MaxTick
67 maxtick = -1
69
70 if options.checkpoint_dir:
71 cptdir = options.checkpoint_dir
72 else:
73 cptdir = getcwd()
74
75 np = options.num_cpus
76 max_checkpoints = options.max_checkpoints
77 switch_cpus = None
78
79 if cpu_class:
80 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
81 for i in xrange(np)]
82
83 for i in xrange(np):
84 switch_cpus[i].system = testsys
85 if not m5.build_env['FULL_SYSTEM']:
86 switch_cpus[i].workload = testsys.cpu[i].workload
87 switch_cpus[i].clock = testsys.cpu[0].clock
68
69 if options.checkpoint_dir:
70 cptdir = options.checkpoint_dir
71 else:
72 cptdir = getcwd()
73
74 np = options.num_cpus
75 max_checkpoints = options.max_checkpoints
76 switch_cpus = None
77
78 if cpu_class:
79 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
80 for i in xrange(np)]
81
82 for i in xrange(np):
83 switch_cpus[i].system = testsys
84 if not m5.build_env['FULL_SYSTEM']:
85 switch_cpus[i].workload = testsys.cpu[i].workload
86 switch_cpus[i].clock = testsys.cpu[0].clock
88 if options.caches:
89 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
90 L1Cache(size = '64kB'))
91 switch_cpus[i].connectMemPorts(testsys.membus)
92
93 root.switch_cpus = switch_cpus
94 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
95
96 if options.standard_switch:
97 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
98 for i in xrange(np)]
99 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
100 for i in xrange(np)]
101
102 for i in xrange(np):
103 switch_cpus[i].system = testsys
104 switch_cpus_1[i].system = testsys
105 if not m5.build_env['FULL_SYSTEM']:
106 switch_cpus[i].workload = testsys.cpu[i].workload
107 switch_cpus_1[i].workload = testsys.cpu[i].workload
108 switch_cpus[i].clock = testsys.cpu[0].clock
109 switch_cpus_1[i].clock = testsys.cpu[0].clock
110
87
88 root.switch_cpus = switch_cpus
89 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
90
91 if options.standard_switch:
92 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
93 for i in xrange(np)]
94 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
95 for i in xrange(np)]
96
97 for i in xrange(np):
98 switch_cpus[i].system = testsys
99 switch_cpus_1[i].system = testsys
100 if not m5.build_env['FULL_SYSTEM']:
101 switch_cpus[i].workload = testsys.cpu[i].workload
102 switch_cpus_1[i].workload = testsys.cpu[i].workload
103 switch_cpus[i].clock = testsys.cpu[0].clock
104 switch_cpus_1[i].clock = testsys.cpu[0].clock
105
111 if options.caches:
112 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
113 L1Cache(size = '64kB'))
114 switch_cpus[i].connectMemPorts(testsys.membus)
115 else:
106 if not options.caches:
116 # O3 CPU must have a cache to work.
117 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
118 L1Cache(size = '64kB'))
119 switch_cpus_1[i].connectMemPorts(testsys.membus)
120
121
107 # O3 CPU must have a cache to work.
108 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
109 L1Cache(size = '64kB'))
110 switch_cpus_1[i].connectMemPorts(testsys.membus)
111
112
122 root.switch_cpus = switch_cpus
123 root.switch_cpus_1 = switch_cpus_1
113 testsys.switch_cpus = switch_cpus
114 testsys.switch_cpus_1 = switch_cpus_1
124 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
125 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
126
127 m5.instantiate(root)
128
129 if options.checkpoint_restore:
130 from os.path import isdir
131 from os import listdir

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145 cpts.sort(lambda a,b: cmp(long(a), long(b)))
146
147 cpt_num = options.checkpoint_restore
148
149 if cpt_num > len(cpts):
150 m5.panic('Checkpoint %d not found' % cpt_num)
151
152 m5.restoreCheckpoint(root,
115 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
116 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
117
118 m5.instantiate(root)
119
120 if options.checkpoint_restore:
121 from os.path import isdir
122 from os import listdir

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136 cpts.sort(lambda a,b: cmp(long(a), long(b)))
137
138 cpt_num = options.checkpoint_restore
139
140 if cpt_num > len(cpts):
141 m5.panic('Checkpoint %d not found' % cpt_num)
142
143 m5.restoreCheckpoint(root,
153 joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]))
144 "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]]))
154
155 if options.standard_switch or cpu_class:
156 exit_event = m5.simulate(10000)
157
158 ## when you change to Timing (or Atomic), you halt the system given
159 ## as argument. When you are finished with the system changes
160 ## (including switchCpus), you must resume the system manually.
161 ## You DON'T need to resume after just switching CPUs if you haven't

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180 when = int(when)
181 period = int(period)
182
183 exit_event = m5.simulate(when)
184 while exit_event.getCause() == "checkpoint":
185 exit_event = m5.simulate(when - m5.curTick())
186
187 if exit_event.getCause() == "simulate() limit reached":
145
146 if options.standard_switch or cpu_class:
147 exit_event = m5.simulate(10000)
148
149 ## when you change to Timing (or Atomic), you halt the system given
150 ## as argument. When you are finished with the system changes
151 ## (including switchCpus), you must resume the system manually.
152 ## You DON'T need to resume after just switching CPUs if you haven't

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171 when = int(when)
172 period = int(period)
173
174 exit_event = m5.simulate(when)
175 while exit_event.getCause() == "checkpoint":
176 exit_event = m5.simulate(when - m5.curTick())
177
178 if exit_event.getCause() == "simulate() limit reached":
188 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
179 m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
189 num_checkpoints += 1
190
191 sim_ticks = when
192 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
193 while num_checkpoints < max_checkpoints:
180 num_checkpoints += 1
181
182 sim_ticks = when
183 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
184 while num_checkpoints < max_checkpoints:
194 if (sim_ticks + period) > maxtick:
185 if (sim_ticks + period) > maxtick and maxtick != -1:
195 exit_event = m5.simulate(maxtick - sim_ticks)
196 exit_cause = exit_event.getCause()
197 break
198 else:
199 exit_event = m5.simulate(period)
200 sim_ticks += period
201 while exit_event.getCause() == "checkpoint":
202 exit_event = m5.simulate(sim_ticks - m5.curTick())
203 if exit_event.getCause() == "simulate() limit reached":
186 exit_event = m5.simulate(maxtick - sim_ticks)
187 exit_cause = exit_event.getCause()
188 break
189 else:
190 exit_event = m5.simulate(period)
191 sim_ticks += period
192 while exit_event.getCause() == "checkpoint":
193 exit_event = m5.simulate(sim_ticks - m5.curTick())
194 if exit_event.getCause() == "simulate() limit reached":
204 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
195 m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
205 num_checkpoints += 1
206
207 else: #no checkpoints being taken via this script
208 exit_event = m5.simulate(maxtick)
209
210 while exit_event.getCause() == "checkpoint":
196 num_checkpoints += 1
197
198 else: #no checkpoints being taken via this script
199 exit_event = m5.simulate(maxtick)
200
201 while exit_event.getCause() == "checkpoint":
211 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
202 m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
212 num_checkpoints += 1
213 if num_checkpoints == max_checkpoints:
214 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
215 break
216
203 num_checkpoints += 1
204 if num_checkpoints == max_checkpoints:
205 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
206 break
207
217 exit_event = m5.simulate(maxtick - m5.curTick())
208 if maxtick == -1:
209 exit_event = m5.simulate(maxtick)
210 else:
211 exit_event = m5.simulate(maxtick - m5.curTick())
212
218 exit_cause = exit_event.getCause()
219
220 if exit_cause == '':
221 exit_cause = exit_event.getCause()
213 exit_cause = exit_event.getCause()
214
215 if exit_cause == '':
216 exit_cause = exit_event.getCause()
222 print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
217 print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause)
223
218