Simulation.py (3480:c1ec938d2920) Simulation.py (3481:14362d3b0756)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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27# Authors: Lisa Hsu
28
29from os import getcwd
30import m5
31from m5.objects import *
32m5.AddToPath('../common')
33from Caches import L1Cache
34
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 18 unchanged lines hidden (view full) ---

27# Authors: Lisa Hsu
28
29from os import getcwd
30import m5
31from m5.objects import *
32m5.AddToPath('../common')
33from Caches import L1Cache
34
35def run(options, root, testsys):
35def setCPUClass(options):
36
37 atomic = False
38 if options.timing:
39 TmpClass = TimingSimpleCPU
40 elif options.detailed:
41 TmpClass = DerivO3CPU
42 else:
43 TmpClass = AtomicSimpleCPU
44 atomic = True
45
46 CPUClass = None
47 test_mem_mode = 'atomic'
48
49 if not atomic:
50 if options.checkpoint_restore:
51 CPUClass = TmpClass
52 TmpClass = AtomicSimpleCPU
53 else:
54 test_mem_mode = 'timing'
55
56 return (TmpClass, test_mem_mode, CPUClass)
57
58
59def run(options, root, testsys, cpu_class):
36 if options.maxtick:
37 maxtick = options.maxtick
38 elif options.maxtime:
39 simtime = int(options.maxtime * root.clock.value)
40 print "simulating for: ", simtime
41 maxtick = simtime
42 else:
43 maxtick = -1
44
45 if options.checkpoint_dir:
46 cptdir = options.checkpoint_dir
47 else:
48 cptdir = getcwd()
49
50 np = options.num_cpus
51 max_checkpoints = options.max_checkpoints
60 if options.maxtick:
61 maxtick = options.maxtick
62 elif options.maxtime:
63 simtime = int(options.maxtime * root.clock.value)
64 print "simulating for: ", simtime
65 maxtick = simtime
66 else:
67 maxtick = -1
68
69 if options.checkpoint_dir:
70 cptdir = options.checkpoint_dir
71 else:
72 cptdir = getcwd()
73
74 np = options.num_cpus
75 max_checkpoints = options.max_checkpoints
76 switch_cpus = None
52
77
78 if cpu_class:
79 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
80 for i in xrange(np)]
81
82 for i in xrange(np):
83 switch_cpus[i].system = testsys
84 if not m5.build_env['FULL_SYSTEM']:
85 switch_cpus[i].workload = testsys.cpu[i].workload
86 switch_cpus[i].clock = testsys.cpu[0].clock
87 if options.caches:
88 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
89 L1Cache(size = '64kB'))
90 switch_cpus[i].connectMemPorts(testsys.membus)
91
92 root.switch_cpus = switch_cpus
93 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
94
53 if options.standard_switch:
54 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
55 for i in xrange(np)]
56 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
57 for i in xrange(np)]
58
59 for i in xrange(np):
60 switch_cpus[i].system = testsys
61 switch_cpus_1[i].system = testsys
62 if not m5.build_env['FULL_SYSTEM']:
63 switch_cpus[i].workload = testsys.cpu[i].workload
64 switch_cpus_1[i].workload = testsys.cpu[i].workload
65 switch_cpus[i].clock = testsys.cpu[0].clock
66 switch_cpus_1[i].clock = testsys.cpu[0].clock
67
95 if options.standard_switch:
96 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
97 for i in xrange(np)]
98 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
99 for i in xrange(np)]
100
101 for i in xrange(np):
102 switch_cpus[i].system = testsys
103 switch_cpus_1[i].system = testsys
104 if not m5.build_env['FULL_SYSTEM']:
105 switch_cpus[i].workload = testsys.cpu[i].workload
106 switch_cpus_1[i].workload = testsys.cpu[i].workload
107 switch_cpus[i].clock = testsys.cpu[0].clock
108 switch_cpus_1[i].clock = testsys.cpu[0].clock
109
68 ## add caches to the warmup timing CPU (which will be
69 ## xferred to O3 when you switch again)
70 if options.caches:
71 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
72 L1Cache(size = '64kB'))
110 if options.caches:
111 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
112 L1Cache(size = '64kB'))
73 else: # O3 CPU must have a cache to work.
113 switch_cpus[i].connectMemPorts(testsys.membus)
114 else:
115 # O3 CPU must have a cache to work.
74 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
75 L1Cache(size = '64kB'))
76 switch_cpus_1[i].connectMemPorts(testsys.membus)
77
116 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
117 L1Cache(size = '64kB'))
118 switch_cpus_1[i].connectMemPorts(testsys.membus)
119
78 switch_cpus[i].connectMemPorts(testsys.membus)
79
80 root.switch_cpus = switch_cpus
81 root.switch_cpus_1 = switch_cpus_1
82 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
83 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
84
85 m5.instantiate(root)
86

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105 cpt_num = options.checkpoint_restore
106
107 if cpt_num > len(cpts):
108 m5.panic('Checkpoint %d not found' % cpt_num)
109
110 m5.restoreCheckpoint(root,
111 "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]]))
112
120
121 root.switch_cpus = switch_cpus
122 root.switch_cpus_1 = switch_cpus_1
123 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
124 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
125
126 m5.instantiate(root)
127

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146 cpt_num = options.checkpoint_restore
147
148 if cpt_num > len(cpts):
149 m5.panic('Checkpoint %d not found' % cpt_num)
150
151 m5.restoreCheckpoint(root,
152 "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]]))
153
113 if options.standard_switch:
154 if options.standard_switch or cpu_class:
114 exit_event = m5.simulate(10000)
115
116 ## when you change to Timing (or Atomic), you halt the system given
117 ## as argument. When you are finished with the system changes
118 ## (including switchCpus), you must resume the system manually.
119 ## You DON'T need to resume after just switching CPUs if you haven't
120 ## changed anything on the system level.
121
122 m5.changeToTiming(testsys)
123 m5.switchCpus(switch_cpu_list)
124 m5.resume(testsys)
125
155 exit_event = m5.simulate(10000)
156
157 ## when you change to Timing (or Atomic), you halt the system given
158 ## as argument. When you are finished with the system changes
159 ## (including switchCpus), you must resume the system manually.
160 ## You DON'T need to resume after just switching CPUs if you haven't
161 ## changed anything on the system level.
162
163 m5.changeToTiming(testsys)
164 m5.switchCpus(switch_cpu_list)
165 m5.resume(testsys)
166
126 exit_event = m5.simulate(options.warmup)
127 m5.switchCpus(switch_cpu_list1)
167 if options.standard_switch:
168 exit_event = m5.simulate(options.warmup)
169 m5.switchCpus(switch_cpu_list1)
128
129 num_checkpoints = 0
130 exit_cause = ''
131
132 ## Checkpoints being taken via the command line at <when> and at subsequent
133 ## periods of <period>. Checkpoint instructions received from the benchmark running
134 ## are ignored and skipped in favor of command line checkpoint instructions.
135 if options.take_checkpoints:

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171 num_checkpoints = 0
172 exit_cause = ''
173
174 ## Checkpoints being taken via the command line at <when> and at subsequent
175 ## periods of <period>. Checkpoint instructions received from the benchmark running
176 ## are ignored and skipped in favor of command line checkpoint instructions.
177 if options.take_checkpoints:

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