Simulation.py (3478:b2372d54182c) Simulation.py (3480:c1ec938d2920)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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59 for i in xrange(np):
60 switch_cpus[i].system = testsys
61 switch_cpus_1[i].system = testsys
62 if not m5.build_env['FULL_SYSTEM']:
63 switch_cpus[i].workload = testsys.cpu[i].workload
64 switch_cpus_1[i].workload = testsys.cpu[i].workload
65 switch_cpus[i].clock = testsys.cpu[0].clock
66 switch_cpus_1[i].clock = testsys.cpu[0].clock
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 50 unchanged lines hidden (view full) ---

59 for i in xrange(np):
60 switch_cpus[i].system = testsys
61 switch_cpus_1[i].system = testsys
62 if not m5.build_env['FULL_SYSTEM']:
63 switch_cpus[i].workload = testsys.cpu[i].workload
64 switch_cpus_1[i].workload = testsys.cpu[i].workload
65 switch_cpus[i].clock = testsys.cpu[0].clock
66 switch_cpus_1[i].clock = testsys.cpu[0].clock
67
68 ## add caches to the warmup timing CPU (which will be
69 ## xferred to O3 when you switch again)
67 if options.caches:
68 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
69 L1Cache(size = '64kB'))
70 if options.caches:
71 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
72 L1Cache(size = '64kB'))
73 else: # O3 CPU must have a cache to work.
74 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
75 L1Cache(size = '64kB'))
76 switch_cpus_1[i].connectMemPorts(testsys.membus)
70
71 switch_cpus[i].connectMemPorts(testsys.membus)
72
73 root.switch_cpus = switch_cpus
74 root.switch_cpus_1 = switch_cpus_1
75 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
76 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
77

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78 switch_cpus[i].connectMemPorts(testsys.membus)
79
80 root.switch_cpus = switch_cpus
81 root.switch_cpus_1 = switch_cpus_1
82 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
83 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
84

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