Simulation.py (3477:eaf445891a4e) Simulation.py (3478:b2372d54182c)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 39 unchanged lines hidden (view full) ---

48 cptdir = getcwd()
49
50 np = options.num_cpus
51 max_checkpoints = options.max_checkpoints
52
53 if options.standard_switch:
54 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
55 for i in xrange(np)]
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 39 unchanged lines hidden (view full) ---

48 cptdir = getcwd()
49
50 np = options.num_cpus
51 max_checkpoints = options.max_checkpoints
52
53 if options.standard_switch:
54 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
55 for i in xrange(np)]
56 switch_cpus1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
56 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
57 for i in xrange(np)]
57 for i in xrange(np)]
58
58 for i in xrange(np):
59 switch_cpus[i].system = testsys
59 for i in xrange(np):
60 switch_cpus[i].system = testsys
60 switch_cpus1[i].system = testsys
61 switch_cpus_1[i].system = testsys
61 if not m5.build_env['FULL_SYSTEM']:
62 switch_cpus[i].workload = testsys.cpu[i].workload
62 if not m5.build_env['FULL_SYSTEM']:
63 switch_cpus[i].workload = testsys.cpu[i].workload
63 switch_cpus1[i].workload = testsys.cpu[i].workload
64 switch_cpus_1[i].workload = testsys.cpu[i].workload
64 switch_cpus[i].clock = testsys.cpu[0].clock
65 switch_cpus[i].clock = testsys.cpu[0].clock
65 switch_cpus1[i].clock = testsys.cpu[0].clock
66 switch_cpus_1[i].clock = testsys.cpu[0].clock
66 if options.caches:
67 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
68 L1Cache(size = '64kB'))
69
70 switch_cpus[i].connectMemPorts(testsys.membus)
67 if options.caches:
68 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
69 L1Cache(size = '64kB'))
70
71 switch_cpus[i].connectMemPorts(testsys.membus)
72
71 root.switch_cpus = switch_cpus
73 root.switch_cpus = switch_cpus
72 root.switch_cpus1 = switch_cpus1
74 root.switch_cpus_1 = switch_cpus_1
73 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
75 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
74 switch_cpu_list1 = [(switch_cpus[i], switch_cpus1[i]) for i in xrange(np)]
76 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
75
76 m5.instantiate(root)
77
78 if options.checkpoint_restore:
79 from os.path import isdir
80 from os import listdir
81 import re
82

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78 m5.instantiate(root)
79
80 if options.checkpoint_restore:
81 from os.path import isdir
82 from os import listdir
83 import re
84

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