1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 37 unchanged lines hidden (view full) ---

46 else:
47 class TmpClass(AtomicSimpleCPU): pass
48 atomic = True
49
50 CPUClass = None
51 test_mem_mode = 'atomic'
52
53 if not atomic:
54 if options.checkpoint_restore or options.fast_forward:
54 if options.checkpoint_restore != None or options.fast_forward:
55 CPUClass = TmpClass
56 class TmpClass(AtomicSimpleCPU): pass
57 else:
58 test_mem_mode = 'timing'
59
60 return (TmpClass, test_mem_mode, CPUClass)
61
62

--- 19 unchanged lines hidden (view full) ---

82 switch_cpus = None
83
84 if cpu_class:
85 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
86 for i in xrange(np)]
87
88 for i in xrange(np):
89 if options.fast_forward:
90 testsys.cpu[i].max_insts_any_thread = options.fast_forward
90 testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
91 switch_cpus[i].system = testsys
92 if not m5.build_env['FULL_SYSTEM']:
93 switch_cpus[i].workload = testsys.cpu[i].workload
94 switch_cpus[i].clock = testsys.cpu[0].clock
95 # simulation period
96 if options.max_inst:
97 switch_cpus[i].max_insts_any_thread = options.max_inst
98
99 testsys.switch_cpus = switch_cpus
100 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
101
102 if options.standard_switch:
103 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
104 for i in xrange(np)]
105 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))

--- 4 unchanged lines hidden (view full) ---

110 switch_cpus_1[i].system = testsys
111 if not m5.build_env['FULL_SYSTEM']:
112 switch_cpus[i].workload = testsys.cpu[i].workload
113 switch_cpus_1[i].workload = testsys.cpu[i].workload
114 switch_cpus[i].clock = testsys.cpu[0].clock
115 switch_cpus_1[i].clock = testsys.cpu[0].clock
116
117 # if restoring, make atomic cpu simulate only a few instructions
115 if options.checkpoint_restore:
118 if options.checkpoint_restore != None:
119 testsys.cpu[i].max_insts_any_thread = 1
120 # Fast forward to specified location if we are not restoring
121 elif options.fast_forward:
119 testsys.cpu[i].max_insts_any_thread = options.fast_forward
122 testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
123 # Fast forward to a simpoint (warning: time consuming)
124 elif options.simpoint:
125 if testsys.cpu[i].workload[0].simpoint == None:
126 m5.panic('simpoint not found')
127 testsys.cpu[i].max_insts_any_thread = \
128 testsys.cpu[i].workload[0].simpoint
129 # No distance specified, just switch
130 else:

--- 14 unchanged lines hidden (view full) ---

145 switch_cpus_1[i].connectMemPorts(testsys.membus)
146
147 testsys.switch_cpus = switch_cpus
148 testsys.switch_cpus_1 = switch_cpus_1
149 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
150 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
151
152 # set the checkpoint in the cpu before m5.instantiate is called
150 if options.take_checkpoints and \
153 if options.take_checkpoints != None and \
154 (options.simpoint or options.at_instruction):
155 offset = int(options.take_checkpoints)
156 # Set an instruction break point
157 if options.simpoint:
158 for i in xrange(np):
159 if testsys.cpu[i].workload[0].simpoint == None:
160 m5.panic('no simpoint for testsys.cpu[%d].workload[0]' % i)
158 checkpoint_inst = testsys.cpu[i].workload[0].simpoint + offset
161 checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset
162 testsys.cpu[i].max_insts_any_thread = checkpoint_inst
163 # used for output below
164 options.take_checkpoints = checkpoint_inst
165 else:
166 options.take_checkpoints = offset
167 # Set all test cpus with the right number of instructions
168 # for the upcoming simulation
169 for i in xrange(np):
170 testsys.cpu[i].max_insts_any_thread = offset
171
169 testsys.cpu_switch_list = cpu_switch_list
170
172 m5.instantiate(root)
173
173 if options.checkpoint_restore:
174 if options.checkpoint_restore != None:
175 from os.path import isdir, exists
176 from os import listdir
177 import re
178
179 if not isdir(cptdir):
180 m5.panic("checkpoint dir %s does not exist!" % cptdir)
181
182 if options.at_instruction:
183 checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % \
184 (options.bench, options.checkpoint_restore))
185 if not exists(checkpoint_dir):
186 m5.panic("Unable to find checkpoint directory %s" % \
187 checkpoint_dir)
188
189 print "Restoring checkpoint ..."
190 m5.restoreCheckpoint(root, checkpoint_dir)
191 print "Done."
192 elif options.simpoint:
193 # assume workload 0 has the simpoint
193 if testsys.cpu[i].workload[0].simpoint == None:
194 if testsys.cpu[0].workload[0].simpoint == None:
195 m5.panic('Unable to find simpoint')
196
197 options.checkpoint_restore += \
197 testsys.cpu[0].workload[0].simpoint
198 int(testsys.cpu[0].workload[0].simpoint)
199
200 checkpoint_dir = joinpath(cptdir, "cpt.%s.%d" % \
201 (options.bench, options.checkpoint_restore))
202 if not exists(checkpoint_dir):
203 m5.panic("Unable to find checkpoint directory %s.%s" % \
204 (options.bench, options.checkpoint_restore))
205
206 print "Restoring checkpoint ..."

--- 64 unchanged lines hidden (view full) ---

271
272 num_checkpoints = 0
273 exit_cause = ''
274
275 # Checkpoints being taken via the command line at <when> and at
276 # subsequent periods of <period>. Checkpoint instructions
277 # received from the benchmark running are ignored and skipped in
278 # favor of command line checkpoint instructions.
278 if options.take_checkpoints:
279 when, period = options.take_checkpoints.split(",", 1)
280 when = int(when)
281 period = int(period)
282
279 if options.take_checkpoints != None :
280 if options.at_instruction or options.simpoint:
284 checkpoint_inst = when
281 checkpoint_inst = int(options.take_checkpoints)
282
283 # maintain correct offset if we restored from some instruction
287 if options.checkpoint_restore:
284 if options.checkpoint_restore != None:
285 checkpoint_inst += options.checkpoint_restore
286
287 print "Creating checkpoint at inst:%d" % (checkpoint_inst)
288 exit_event = m5.simulate()
289 print "exit cause = %s" % (exit_event.getCause())
290
291 # skip checkpoint instructions should they exist
292 while exit_event.getCause() == "checkpoint":

--- 4 unchanged lines hidden (view full) ---

297 m5.checkpoint(root, joinpath(cptdir, "cpt.%s.%d" % \
298 (options.bench, checkpoint_inst)))
299 print "Checkpoint written."
300 num_checkpoints += 1
301
302 if exit_event.getCause() == "user interrupt received":
303 exit_cause = exit_event.getCause();
304 else:
305 when, period = options.take_checkpoints.split(",", 1)
306 when = int(when)
307 period = int(period)
308
309 exit_event = m5.simulate(when)
310 while exit_event.getCause() == "checkpoint":
311 exit_event = m5.simulate(when - m5.curTick())
312
313 if exit_event.getCause() == "simulate() limit reached":
314 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
315 num_checkpoints += 1
316

--- 40 unchanged lines hidden ---