1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 53 unchanged lines hidden (view full) --- 62 switch_cpus[i].workload = testsys.cpu[i].workload 63 switch_cpus1[i].workload = testsys.cpu[i].workload 64 switch_cpus[i].clock = testsys.cpu[0].clock 65 switch_cpus1[i].clock = testsys.cpu[0].clock 66 if options.caches: 67 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 68 L1Cache(size = '64kB')) 69 |
70 switch_cpus[i].connectMemPorts(testsys.membus) 71 root.switch_cpus = switch_cpus 72 root.switch_cpus1 = switch_cpus1 73 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 74 switch_cpu_list1 = [(switch_cpus[i], switch_cpus1[i]) for i in xrange(np)] 75 76 m5.instantiate(root) 77 --- 98 unchanged lines hidden --- |