35c35,59
< def run(options, root, testsys):
---
> def setCPUClass(options):
>
> atomic = False
> if options.timing:
> TmpClass = TimingSimpleCPU
> elif options.detailed:
> TmpClass = DerivO3CPU
> else:
> TmpClass = AtomicSimpleCPU
> atomic = True
>
> CPUClass = None
> test_mem_mode = 'atomic'
>
> if not atomic:
> if options.checkpoint_restore:
> CPUClass = TmpClass
> TmpClass = AtomicSimpleCPU
> else:
> test_mem_mode = 'timing'
>
> return (TmpClass, test_mem_mode, CPUClass)
>
>
> def run(options, root, testsys, cpu_class):
51a76
> switch_cpus = None
52a78,94
> if cpu_class:
> switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
> for i in xrange(np)]
>
> for i in xrange(np):
> switch_cpus[i].system = testsys
> if not m5.build_env['FULL_SYSTEM']:
> switch_cpus[i].workload = testsys.cpu[i].workload
> switch_cpus[i].clock = testsys.cpu[0].clock
> if options.caches:
> switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
> L1Cache(size = '64kB'))
> switch_cpus[i].connectMemPorts(testsys.membus)
>
> root.switch_cpus = switch_cpus
> switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
>
68,69d109
< ## add caches to the warmup timing CPU (which will be
< ## xferred to O3 when you switch again)
73c113,115
< else: # O3 CPU must have a cache to work.
---
> switch_cpus[i].connectMemPorts(testsys.membus)
> else:
> # O3 CPU must have a cache to work.
78d119
< switch_cpus[i].connectMemPorts(testsys.membus)
113c154
< if options.standard_switch:
---
> if options.standard_switch or cpu_class:
126,127c167,169
< exit_event = m5.simulate(options.warmup)
< m5.switchCpus(switch_cpu_list1)
---
> if options.standard_switch:
> exit_event = m5.simulate(options.warmup)
> m5.switchCpus(switch_cpu_list1)