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>
> ## add caches to the warmup timing CPU (which will be
> ## xferred to O3 when you switch again)
69a73,76
> else: # O3 CPU must have a cache to work.
> switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
> L1Cache(size = '64kB'))
> switch_cpus_1[i].connectMemPorts(testsys.membus)