1# Copyright (c) 2006-2007 The Regents of The University of Michigan
| 1# Copyright (c) 2006-2008 The Regents of The University of Michigan
|
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29from os import getcwd
30from os.path import join as joinpath
31import m5
32from m5.objects import *
33m5.AddToPath('../common')
34from Caches import L1Cache
35
36def setCPUClass(options):
37
38 atomic = False
39 if options.timing:
| 2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29from os import getcwd
30from os.path import join as joinpath
31import m5
32from m5.objects import *
33m5.AddToPath('../common')
34from Caches import L1Cache
35
36def setCPUClass(options):
37
38 atomic = False
39 if options.timing:
|
40 TmpClass = TimingSimpleCPU
| 40 class TmpClass(TimingSimpleCPU): pass
|
41 elif options.detailed:
42 if not options.caches:
43 print "O3 CPU must be used with caches"
44 sys.exit(1)
| 41 elif options.detailed:
42 if not options.caches:
43 print "O3 CPU must be used with caches"
44 sys.exit(1)
|
45 TmpClass = DerivO3CPU
| 45 class TmpClass(DerivO3CPU): pass
|
46 else:
| 46 else:
|
47 TmpClass = AtomicSimpleCPU
| 47 class TmpClass(AtomicSimpleCPU): pass
|
48 atomic = True
49
50 CPUClass = None
51 test_mem_mode = 'atomic'
52
53 if not atomic:
54 if options.checkpoint_restore:
55 CPUClass = TmpClass
| 48 atomic = True
49
50 CPUClass = None
51 test_mem_mode = 'atomic'
52
53 if not atomic:
54 if options.checkpoint_restore:
55 CPUClass = TmpClass
|
56 TmpClass = AtomicSimpleCPU
| 56 class TmpClass(AtomicSimpleCPU): pass
|
57 else:
58 test_mem_mode = 'timing'
59
60 return (TmpClass, test_mem_mode, CPUClass)
61
62
63def run(options, root, testsys, cpu_class):
64 if options.maxtick:
65 maxtick = options.maxtick
66 elif options.maxtime:
67 simtime = m5.ticks.seconds(simtime)
68 print "simulating for: ", simtime
69 maxtick = simtime
70 else:
71 maxtick = m5.MaxTick
72
73 if options.checkpoint_dir:
74 cptdir = options.checkpoint_dir
75 elif m5.options.outdir:
76 cptdir = m5.options.outdir
77 else:
78 cptdir = getcwd()
79
80 np = options.num_cpus
81 max_checkpoints = options.max_checkpoints
82 switch_cpus = None
83
84 if cpu_class:
85 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
86 for i in xrange(np)]
87
88 for i in xrange(np):
89 switch_cpus[i].system = testsys
90 if not m5.build_env['FULL_SYSTEM']:
91 switch_cpus[i].workload = testsys.cpu[i].workload
92 switch_cpus[i].clock = testsys.cpu[0].clock
93
94 testsys.switch_cpus = switch_cpus
95 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
96
97 if options.standard_switch:
98 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
99 for i in xrange(np)]
100 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
101 for i in xrange(np)]
102
103 for i in xrange(np):
104 switch_cpus[i].system = testsys
105 switch_cpus_1[i].system = testsys
106 if not m5.build_env['FULL_SYSTEM']:
107 switch_cpus[i].workload = testsys.cpu[i].workload
108 switch_cpus_1[i].workload = testsys.cpu[i].workload
109 switch_cpus[i].clock = testsys.cpu[0].clock
110 switch_cpus_1[i].clock = testsys.cpu[0].clock
111
112 if not options.caches:
113 # O3 CPU must have a cache to work.
114 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
115 L1Cache(size = '64kB'))
116 switch_cpus_1[i].connectMemPorts(testsys.membus)
117
118
119 testsys.switch_cpus = switch_cpus
120 testsys.switch_cpus_1 = switch_cpus_1
121 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
122 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
123
124 m5.instantiate(root)
125
126 if options.checkpoint_restore:
127 from os.path import isdir
128 from os import listdir
129 import re
130
131 if not isdir(cptdir):
132 m5.panic("checkpoint dir %s does not exist!" % cptdir)
133
134 dirs = listdir(cptdir)
135 expr = re.compile('cpt\.([0-9]*)')
136 cpts = []
137 for dir in dirs:
138 match = expr.match(dir)
139 if match:
140 cpts.append(match.group(1))
141
142 cpts.sort(lambda a,b: cmp(long(a), long(b)))
143
144 cpt_num = options.checkpoint_restore
145
146 if cpt_num > len(cpts):
147 m5.panic('Checkpoint %d not found' % cpt_num)
148
149 ## Adjust max tick based on our starting tick
150 maxtick = maxtick - int(cpts[cpt_num - 1])
151
152 ## Restore the checkpoint
153 m5.restoreCheckpoint(root,
154 joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]))
155
156 if options.standard_switch or cpu_class:
157 exit_event = m5.simulate(10000)
158
159 ## when you change to Timing (or Atomic), you halt the system given
160 ## as argument. When you are finished with the system changes
161 ## (including switchCpus), you must resume the system manually.
162 ## You DON'T need to resume after just switching CPUs if you haven't
163 ## changed anything on the system level.
164
165 m5.changeToTiming(testsys)
166 m5.switchCpus(switch_cpu_list)
167 m5.resume(testsys)
168
169 if options.standard_switch:
170 exit_event = m5.simulate(options.warmup)
171 m5.drain(testsys)
172 m5.switchCpus(switch_cpu_list1)
173 m5.resume(testsys)
174
175 num_checkpoints = 0
176 exit_cause = ''
177
178 ## Checkpoints being taken via the command line at <when> and at subsequent
179 ## periods of <period>. Checkpoint instructions received from the benchmark running
180 ## are ignored and skipped in favor of command line checkpoint instructions.
181 if options.take_checkpoints:
182 [when, period] = options.take_checkpoints.split(",", 1)
183 when = int(when)
184 period = int(period)
185
186 exit_event = m5.simulate(when)
187 while exit_event.getCause() == "checkpoint":
188 exit_event = m5.simulate(when - m5.curTick())
189
190 if exit_event.getCause() == "simulate() limit reached":
191 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
192 num_checkpoints += 1
193
194 sim_ticks = when
195 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
196 while num_checkpoints < max_checkpoints and \
197 exit_event.getCause() == "simulate() limit reached":
198 if (sim_ticks + period) > maxtick:
199 exit_event = m5.simulate(maxtick - sim_ticks)
200 exit_cause = exit_event.getCause()
201 break
202 else:
203 exit_event = m5.simulate(period)
204 sim_ticks += period
205 while exit_event.getCause() == "checkpoint":
206 exit_event = m5.simulate(sim_ticks - m5.curTick())
207 if exit_event.getCause() == "simulate() limit reached":
208 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
209 num_checkpoints += 1
210
211 if exit_event.getCause() != "simulate() limit reached":
212 exit_cause = exit_event.getCause();
213
214
215 else: #no checkpoints being taken via this script
216 exit_event = m5.simulate(maxtick)
217
218 while exit_event.getCause() == "checkpoint":
219 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
220 num_checkpoints += 1
221 if num_checkpoints == max_checkpoints:
222 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
223 break
224
225 exit_event = m5.simulate(maxtick - m5.curTick())
226 exit_cause = exit_event.getCause()
227
228 if exit_cause == '':
229 exit_cause = exit_event.getCause()
230 print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause)
231
| 57 else:
58 test_mem_mode = 'timing'
59
60 return (TmpClass, test_mem_mode, CPUClass)
61
62
63def run(options, root, testsys, cpu_class):
64 if options.maxtick:
65 maxtick = options.maxtick
66 elif options.maxtime:
67 simtime = m5.ticks.seconds(simtime)
68 print "simulating for: ", simtime
69 maxtick = simtime
70 else:
71 maxtick = m5.MaxTick
72
73 if options.checkpoint_dir:
74 cptdir = options.checkpoint_dir
75 elif m5.options.outdir:
76 cptdir = m5.options.outdir
77 else:
78 cptdir = getcwd()
79
80 np = options.num_cpus
81 max_checkpoints = options.max_checkpoints
82 switch_cpus = None
83
84 if cpu_class:
85 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
86 for i in xrange(np)]
87
88 for i in xrange(np):
89 switch_cpus[i].system = testsys
90 if not m5.build_env['FULL_SYSTEM']:
91 switch_cpus[i].workload = testsys.cpu[i].workload
92 switch_cpus[i].clock = testsys.cpu[0].clock
93
94 testsys.switch_cpus = switch_cpus
95 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
96
97 if options.standard_switch:
98 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
99 for i in xrange(np)]
100 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
101 for i in xrange(np)]
102
103 for i in xrange(np):
104 switch_cpus[i].system = testsys
105 switch_cpus_1[i].system = testsys
106 if not m5.build_env['FULL_SYSTEM']:
107 switch_cpus[i].workload = testsys.cpu[i].workload
108 switch_cpus_1[i].workload = testsys.cpu[i].workload
109 switch_cpus[i].clock = testsys.cpu[0].clock
110 switch_cpus_1[i].clock = testsys.cpu[0].clock
111
112 if not options.caches:
113 # O3 CPU must have a cache to work.
114 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
115 L1Cache(size = '64kB'))
116 switch_cpus_1[i].connectMemPorts(testsys.membus)
117
118
119 testsys.switch_cpus = switch_cpus
120 testsys.switch_cpus_1 = switch_cpus_1
121 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
122 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
123
124 m5.instantiate(root)
125
126 if options.checkpoint_restore:
127 from os.path import isdir
128 from os import listdir
129 import re
130
131 if not isdir(cptdir):
132 m5.panic("checkpoint dir %s does not exist!" % cptdir)
133
134 dirs = listdir(cptdir)
135 expr = re.compile('cpt\.([0-9]*)')
136 cpts = []
137 for dir in dirs:
138 match = expr.match(dir)
139 if match:
140 cpts.append(match.group(1))
141
142 cpts.sort(lambda a,b: cmp(long(a), long(b)))
143
144 cpt_num = options.checkpoint_restore
145
146 if cpt_num > len(cpts):
147 m5.panic('Checkpoint %d not found' % cpt_num)
148
149 ## Adjust max tick based on our starting tick
150 maxtick = maxtick - int(cpts[cpt_num - 1])
151
152 ## Restore the checkpoint
153 m5.restoreCheckpoint(root,
154 joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]))
155
156 if options.standard_switch or cpu_class:
157 exit_event = m5.simulate(10000)
158
159 ## when you change to Timing (or Atomic), you halt the system given
160 ## as argument. When you are finished with the system changes
161 ## (including switchCpus), you must resume the system manually.
162 ## You DON'T need to resume after just switching CPUs if you haven't
163 ## changed anything on the system level.
164
165 m5.changeToTiming(testsys)
166 m5.switchCpus(switch_cpu_list)
167 m5.resume(testsys)
168
169 if options.standard_switch:
170 exit_event = m5.simulate(options.warmup)
171 m5.drain(testsys)
172 m5.switchCpus(switch_cpu_list1)
173 m5.resume(testsys)
174
175 num_checkpoints = 0
176 exit_cause = ''
177
178 ## Checkpoints being taken via the command line at <when> and at subsequent
179 ## periods of <period>. Checkpoint instructions received from the benchmark running
180 ## are ignored and skipped in favor of command line checkpoint instructions.
181 if options.take_checkpoints:
182 [when, period] = options.take_checkpoints.split(",", 1)
183 when = int(when)
184 period = int(period)
185
186 exit_event = m5.simulate(when)
187 while exit_event.getCause() == "checkpoint":
188 exit_event = m5.simulate(when - m5.curTick())
189
190 if exit_event.getCause() == "simulate() limit reached":
191 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
192 num_checkpoints += 1
193
194 sim_ticks = when
195 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
196 while num_checkpoints < max_checkpoints and \
197 exit_event.getCause() == "simulate() limit reached":
198 if (sim_ticks + period) > maxtick:
199 exit_event = m5.simulate(maxtick - sim_ticks)
200 exit_cause = exit_event.getCause()
201 break
202 else:
203 exit_event = m5.simulate(period)
204 sim_ticks += period
205 while exit_event.getCause() == "checkpoint":
206 exit_event = m5.simulate(sim_ticks - m5.curTick())
207 if exit_event.getCause() == "simulate() limit reached":
208 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
209 num_checkpoints += 1
210
211 if exit_event.getCause() != "simulate() limit reached":
212 exit_cause = exit_event.getCause();
213
214
215 else: #no checkpoints being taken via this script
216 exit_event = m5.simulate(maxtick)
217
218 while exit_event.getCause() == "checkpoint":
219 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
220 num_checkpoints += 1
221 if num_checkpoints == max_checkpoints:
222 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
223 break
224
225 exit_event = m5.simulate(maxtick - m5.curTick())
226 exit_cause = exit_event.getCause()
227
228 if exit_cause == '':
229 exit_cause = exit_event.getCause()
230 print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause)
231
|