1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29from os import getcwd
| 1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29from os import getcwd
|
| 30from os.path import join as joinpath
|
30import m5
31from m5.objects import *
32m5.AddToPath('../common')
33from Caches import L1Cache
34
35def setCPUClass(options):
36
37 atomic = False
38 if options.timing:
39 TmpClass = TimingSimpleCPU
40 elif options.detailed:
41 TmpClass = DerivO3CPU
42 else:
43 TmpClass = AtomicSimpleCPU
44 atomic = True
45
46 CPUClass = None
47 test_mem_mode = 'atomic'
48
49 if not atomic:
50 if options.checkpoint_restore:
51 CPUClass = TmpClass
52 TmpClass = AtomicSimpleCPU
53 else:
54 test_mem_mode = 'timing'
55
56 return (TmpClass, test_mem_mode, CPUClass)
57
58
59def run(options, root, testsys, cpu_class):
60 if options.maxtick:
61 maxtick = options.maxtick
62 elif options.maxtime:
63 simtime = int(options.maxtime * root.clock.value)
64 print "simulating for: ", simtime
65 maxtick = simtime
66 else:
| 31import m5
32from m5.objects import *
33m5.AddToPath('../common')
34from Caches import L1Cache
35
36def setCPUClass(options):
37
38 atomic = False
39 if options.timing:
40 TmpClass = TimingSimpleCPU
41 elif options.detailed:
42 TmpClass = DerivO3CPU
43 else:
44 TmpClass = AtomicSimpleCPU
45 atomic = True
46
47 CPUClass = None
48 test_mem_mode = 'atomic'
49
50 if not atomic:
51 if options.checkpoint_restore:
52 CPUClass = TmpClass
53 TmpClass = AtomicSimpleCPU
54 else:
55 test_mem_mode = 'timing'
56
57 return (TmpClass, test_mem_mode, CPUClass)
58
59
60def run(options, root, testsys, cpu_class):
61 if options.maxtick:
62 maxtick = options.maxtick
63 elif options.maxtime:
64 simtime = int(options.maxtime * root.clock.value)
65 print "simulating for: ", simtime
66 maxtick = simtime
67 else:
|
67 maxtick = -1
| 68 maxtick = m5.MaxTick
|
68
69 if options.checkpoint_dir:
70 cptdir = options.checkpoint_dir
71 else:
72 cptdir = getcwd()
73
74 np = options.num_cpus
75 max_checkpoints = options.max_checkpoints
76 switch_cpus = None
77
78 if cpu_class:
79 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
80 for i in xrange(np)]
81
82 for i in xrange(np):
83 switch_cpus[i].system = testsys
84 if not m5.build_env['FULL_SYSTEM']:
85 switch_cpus[i].workload = testsys.cpu[i].workload
86 switch_cpus[i].clock = testsys.cpu[0].clock
87
88 root.switch_cpus = switch_cpus
89 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
90
91 if options.standard_switch:
92 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
93 for i in xrange(np)]
94 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
95 for i in xrange(np)]
96
97 for i in xrange(np):
98 switch_cpus[i].system = testsys
99 switch_cpus_1[i].system = testsys
100 if not m5.build_env['FULL_SYSTEM']:
101 switch_cpus[i].workload = testsys.cpu[i].workload
102 switch_cpus_1[i].workload = testsys.cpu[i].workload
103 switch_cpus[i].clock = testsys.cpu[0].clock
104 switch_cpus_1[i].clock = testsys.cpu[0].clock
105
106 if not options.caches:
107 # O3 CPU must have a cache to work.
108 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
109 L1Cache(size = '64kB'))
110 switch_cpus_1[i].connectMemPorts(testsys.membus)
111
112
113 testsys.switch_cpus = switch_cpus
114 testsys.switch_cpus_1 = switch_cpus_1
115 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
116 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
117
118 m5.instantiate(root)
119
120 if options.checkpoint_restore:
121 from os.path import isdir
122 from os import listdir
123 import re
124
125 if not isdir(cptdir):
126 m5.panic("checkpoint dir %s does not exist!" % cptdir)
127
128 dirs = listdir(cptdir)
129 expr = re.compile('cpt.([0-9]*)')
130 cpts = []
131 for dir in dirs:
132 match = expr.match(dir)
133 if match:
134 cpts.append(match.group(1))
135
136 cpts.sort(lambda a,b: cmp(long(a), long(b)))
137
138 cpt_num = options.checkpoint_restore
139
140 if cpt_num > len(cpts):
141 m5.panic('Checkpoint %d not found' % cpt_num)
142
143 m5.restoreCheckpoint(root,
| 69
70 if options.checkpoint_dir:
71 cptdir = options.checkpoint_dir
72 else:
73 cptdir = getcwd()
74
75 np = options.num_cpus
76 max_checkpoints = options.max_checkpoints
77 switch_cpus = None
78
79 if cpu_class:
80 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
81 for i in xrange(np)]
82
83 for i in xrange(np):
84 switch_cpus[i].system = testsys
85 if not m5.build_env['FULL_SYSTEM']:
86 switch_cpus[i].workload = testsys.cpu[i].workload
87 switch_cpus[i].clock = testsys.cpu[0].clock
88
89 root.switch_cpus = switch_cpus
90 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
91
92 if options.standard_switch:
93 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
94 for i in xrange(np)]
95 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
96 for i in xrange(np)]
97
98 for i in xrange(np):
99 switch_cpus[i].system = testsys
100 switch_cpus_1[i].system = testsys
101 if not m5.build_env['FULL_SYSTEM']:
102 switch_cpus[i].workload = testsys.cpu[i].workload
103 switch_cpus_1[i].workload = testsys.cpu[i].workload
104 switch_cpus[i].clock = testsys.cpu[0].clock
105 switch_cpus_1[i].clock = testsys.cpu[0].clock
106
107 if not options.caches:
108 # O3 CPU must have a cache to work.
109 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
110 L1Cache(size = '64kB'))
111 switch_cpus_1[i].connectMemPorts(testsys.membus)
112
113
114 testsys.switch_cpus = switch_cpus
115 testsys.switch_cpus_1 = switch_cpus_1
116 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
117 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
118
119 m5.instantiate(root)
120
121 if options.checkpoint_restore:
122 from os.path import isdir
123 from os import listdir
124 import re
125
126 if not isdir(cptdir):
127 m5.panic("checkpoint dir %s does not exist!" % cptdir)
128
129 dirs = listdir(cptdir)
130 expr = re.compile('cpt.([0-9]*)')
131 cpts = []
132 for dir in dirs:
133 match = expr.match(dir)
134 if match:
135 cpts.append(match.group(1))
136
137 cpts.sort(lambda a,b: cmp(long(a), long(b)))
138
139 cpt_num = options.checkpoint_restore
140
141 if cpt_num > len(cpts):
142 m5.panic('Checkpoint %d not found' % cpt_num)
143
144 m5.restoreCheckpoint(root,
|
144 "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]]))
| 145 joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]))
|
145
146 if options.standard_switch or cpu_class:
147 exit_event = m5.simulate(10000)
148
149 ## when you change to Timing (or Atomic), you halt the system given
150 ## as argument. When you are finished with the system changes
151 ## (including switchCpus), you must resume the system manually.
152 ## You DON'T need to resume after just switching CPUs if you haven't
153 ## changed anything on the system level.
154
155 m5.changeToTiming(testsys)
156 m5.switchCpus(switch_cpu_list)
157 m5.resume(testsys)
158
159 if options.standard_switch:
160 exit_event = m5.simulate(options.warmup)
161 m5.switchCpus(switch_cpu_list1)
162
163 num_checkpoints = 0
164 exit_cause = ''
165
166 ## Checkpoints being taken via the command line at <when> and at subsequent
167 ## periods of <period>. Checkpoint instructions received from the benchmark running
168 ## are ignored and skipped in favor of command line checkpoint instructions.
169 if options.take_checkpoints:
170 [when, period] = options.take_checkpoints.split(",", 1)
171 when = int(when)
172 period = int(period)
173
174 exit_event = m5.simulate(when)
175 while exit_event.getCause() == "checkpoint":
176 exit_event = m5.simulate(when - m5.curTick())
177
178 if exit_event.getCause() == "simulate() limit reached":
| 146
147 if options.standard_switch or cpu_class:
148 exit_event = m5.simulate(10000)
149
150 ## when you change to Timing (or Atomic), you halt the system given
151 ## as argument. When you are finished with the system changes
152 ## (including switchCpus), you must resume the system manually.
153 ## You DON'T need to resume after just switching CPUs if you haven't
154 ## changed anything on the system level.
155
156 m5.changeToTiming(testsys)
157 m5.switchCpus(switch_cpu_list)
158 m5.resume(testsys)
159
160 if options.standard_switch:
161 exit_event = m5.simulate(options.warmup)
162 m5.switchCpus(switch_cpu_list1)
163
164 num_checkpoints = 0
165 exit_cause = ''
166
167 ## Checkpoints being taken via the command line at <when> and at subsequent
168 ## periods of <period>. Checkpoint instructions received from the benchmark running
169 ## are ignored and skipped in favor of command line checkpoint instructions.
170 if options.take_checkpoints:
171 [when, period] = options.take_checkpoints.split(",", 1)
172 when = int(when)
173 period = int(period)
174
175 exit_event = m5.simulate(when)
176 while exit_event.getCause() == "checkpoint":
177 exit_event = m5.simulate(when - m5.curTick())
178
179 if exit_event.getCause() == "simulate() limit reached":
|
179 m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
| 180 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
|
180 num_checkpoints += 1
181
182 sim_ticks = when
183 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
184 while num_checkpoints < max_checkpoints:
| 181 num_checkpoints += 1
182
183 sim_ticks = when
184 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
185 while num_checkpoints < max_checkpoints:
|
185 if (sim_ticks + period) > maxtick and maxtick != -1:
| 186 if (sim_ticks + period) > maxtick:
|
186 exit_event = m5.simulate(maxtick - sim_ticks)
187 exit_cause = exit_event.getCause()
188 break
189 else:
190 exit_event = m5.simulate(period)
191 sim_ticks += period
192 while exit_event.getCause() == "checkpoint":
193 exit_event = m5.simulate(sim_ticks - m5.curTick())
194 if exit_event.getCause() == "simulate() limit reached":
| 187 exit_event = m5.simulate(maxtick - sim_ticks)
188 exit_cause = exit_event.getCause()
189 break
190 else:
191 exit_event = m5.simulate(period)
192 sim_ticks += period
193 while exit_event.getCause() == "checkpoint":
194 exit_event = m5.simulate(sim_ticks - m5.curTick())
195 if exit_event.getCause() == "simulate() limit reached":
|
195 m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
| 196 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
|
196 num_checkpoints += 1
197
198 else: #no checkpoints being taken via this script
199 exit_event = m5.simulate(maxtick)
200
201 while exit_event.getCause() == "checkpoint":
| 197 num_checkpoints += 1
198
199 else: #no checkpoints being taken via this script
200 exit_event = m5.simulate(maxtick)
201
202 while exit_event.getCause() == "checkpoint":
|
202 m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
| 203 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
|
203 num_checkpoints += 1
204 if num_checkpoints == max_checkpoints:
205 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
206 break
207
| 204 num_checkpoints += 1
205 if num_checkpoints == max_checkpoints:
206 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
207 break
208
|
208 if maxtick == -1:
209 exit_event = m5.simulate(maxtick)
210 else:
211 exit_event = m5.simulate(maxtick - m5.curTick())
212
| 209 exit_event = m5.simulate(maxtick - m5.curTick())
|
213 exit_cause = exit_event.getCause()
214
215 if exit_cause == '':
216 exit_cause = exit_event.getCause()
217 print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause)
218
| 210 exit_cause = exit_event.getCause()
211
212 if exit_cause == '':
213 exit_cause = exit_event.getCause()
214 print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause)
215
|