1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29from os import getcwd
30import m5
31from m5.objects import *
32m5.AddToPath('../common')
33from Caches import L1Cache
34
35def run(options, root, testsys):
36 if options.maxtick:
37 maxtick = options.maxtick
38 elif options.maxtime:
39 simtime = int(options.maxtime * root.clock.value)
40 print "simulating for: ", simtime
41 maxtick = simtime
42 else:
43 maxtick = -1
44
45 if options.checkpoint_dir:
46 cptdir = options.checkpoint_dir
47 else:
48 cptdir = getcwd()
49
50 np = options.num_cpus
51 max_checkpoints = options.max_checkpoints
52
53 if options.standard_switch:
54 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
55 for i in xrange(np)]
56 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
57 for i in xrange(np)]
58
59 for i in xrange(np):
60 switch_cpus[i].system = testsys
61 switch_cpus_1[i].system = testsys
62 if not m5.build_env['FULL_SYSTEM']:
63 switch_cpus[i].workload = testsys.cpu[i].workload
64 switch_cpus_1[i].workload = testsys.cpu[i].workload
65 switch_cpus[i].clock = testsys.cpu[0].clock
66 switch_cpus_1[i].clock = testsys.cpu[0].clock
| 1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29from os import getcwd
30import m5
31from m5.objects import *
32m5.AddToPath('../common')
33from Caches import L1Cache
34
35def run(options, root, testsys):
36 if options.maxtick:
37 maxtick = options.maxtick
38 elif options.maxtime:
39 simtime = int(options.maxtime * root.clock.value)
40 print "simulating for: ", simtime
41 maxtick = simtime
42 else:
43 maxtick = -1
44
45 if options.checkpoint_dir:
46 cptdir = options.checkpoint_dir
47 else:
48 cptdir = getcwd()
49
50 np = options.num_cpus
51 max_checkpoints = options.max_checkpoints
52
53 if options.standard_switch:
54 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
55 for i in xrange(np)]
56 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
57 for i in xrange(np)]
58
59 for i in xrange(np):
60 switch_cpus[i].system = testsys
61 switch_cpus_1[i].system = testsys
62 if not m5.build_env['FULL_SYSTEM']:
63 switch_cpus[i].workload = testsys.cpu[i].workload
64 switch_cpus_1[i].workload = testsys.cpu[i].workload
65 switch_cpus[i].clock = testsys.cpu[0].clock
66 switch_cpus_1[i].clock = testsys.cpu[0].clock
|
| 67
68 ## add caches to the warmup timing CPU (which will be
69 ## xferred to O3 when you switch again)
|
67 if options.caches:
68 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
69 L1Cache(size = '64kB'))
| 70 if options.caches:
71 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
72 L1Cache(size = '64kB'))
|
| 73 else: # O3 CPU must have a cache to work.
74 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
75 L1Cache(size = '64kB'))
76 switch_cpus_1[i].connectMemPorts(testsys.membus)
|
70
71 switch_cpus[i].connectMemPorts(testsys.membus)
72
73 root.switch_cpus = switch_cpus
74 root.switch_cpus_1 = switch_cpus_1
75 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
76 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
77
78 m5.instantiate(root)
79
80 if options.checkpoint_restore:
81 from os.path import isdir
82 from os import listdir
83 import re
84
85 if not isdir(cptdir):
86 m5.panic("checkpoint dir %s does not exist!" % cptdir)
87
88 dirs = listdir(cptdir)
89 expr = re.compile('cpt.([0-9]*)')
90 cpts = []
91 for dir in dirs:
92 match = expr.match(dir)
93 if match:
94 cpts.append(match.group(1))
95
96 cpts.sort(lambda a,b: cmp(long(a), long(b)))
97
98 cpt_num = options.checkpoint_restore
99
100 if cpt_num > len(cpts):
101 m5.panic('Checkpoint %d not found' % cpt_num)
102
103 m5.restoreCheckpoint(root,
104 "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]]))
105
106 if options.standard_switch:
107 exit_event = m5.simulate(10000)
108
109 ## when you change to Timing (or Atomic), you halt the system given
110 ## as argument. When you are finished with the system changes
111 ## (including switchCpus), you must resume the system manually.
112 ## You DON'T need to resume after just switching CPUs if you haven't
113 ## changed anything on the system level.
114
115 m5.changeToTiming(testsys)
116 m5.switchCpus(switch_cpu_list)
117 m5.resume(testsys)
118
119 exit_event = m5.simulate(options.warmup)
120 m5.switchCpus(switch_cpu_list1)
121
122 num_checkpoints = 0
123 exit_cause = ''
124
125 ## Checkpoints being taken via the command line at <when> and at subsequent
126 ## periods of <period>. Checkpoint instructions received from the benchmark running
127 ## are ignored and skipped in favor of command line checkpoint instructions.
128 if options.take_checkpoints:
129 [when, period] = options.take_checkpoints.split(",", 1)
130 when = int(when)
131 period = int(period)
132
133 exit_event = m5.simulate(when)
134 while exit_event.getCause() == "checkpoint":
135 exit_event = m5.simulate(when - m5.curTick())
136
137 if exit_event.getCause() == "simulate() limit reached":
138 m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
139 num_checkpoints += 1
140
141 sim_ticks = when
142 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
143 while num_checkpoints < max_checkpoints:
144 if (sim_ticks + period) > maxtick and maxtick != -1:
145 exit_event = m5.simulate(maxtick - sim_ticks)
146 exit_cause = exit_event.getCause()
147 break
148 else:
149 exit_event = m5.simulate(period)
150 sim_ticks += period
151 while exit_event.getCause() == "checkpoint":
152 exit_event = m5.simulate(sim_ticks - m5.curTick())
153 if exit_event.getCause() == "simulate() limit reached":
154 m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
155 num_checkpoints += 1
156
157 else: #no checkpoints being taken via this script
158 exit_event = m5.simulate(maxtick)
159
160 while exit_event.getCause() == "checkpoint":
161 m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
162 num_checkpoints += 1
163 if num_checkpoints == max_checkpoints:
164 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
165 break
166
167 if maxtick == -1:
168 exit_event = m5.simulate(maxtick)
169 else:
170 exit_event = m5.simulate(maxtick - m5.curTick())
171
172 exit_cause = exit_event.getCause()
173
174 if exit_cause == '':
175 exit_cause = exit_event.getCause()
176 print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
177
| 77
78 switch_cpus[i].connectMemPorts(testsys.membus)
79
80 root.switch_cpus = switch_cpus
81 root.switch_cpus_1 = switch_cpus_1
82 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
83 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
84
85 m5.instantiate(root)
86
87 if options.checkpoint_restore:
88 from os.path import isdir
89 from os import listdir
90 import re
91
92 if not isdir(cptdir):
93 m5.panic("checkpoint dir %s does not exist!" % cptdir)
94
95 dirs = listdir(cptdir)
96 expr = re.compile('cpt.([0-9]*)')
97 cpts = []
98 for dir in dirs:
99 match = expr.match(dir)
100 if match:
101 cpts.append(match.group(1))
102
103 cpts.sort(lambda a,b: cmp(long(a), long(b)))
104
105 cpt_num = options.checkpoint_restore
106
107 if cpt_num > len(cpts):
108 m5.panic('Checkpoint %d not found' % cpt_num)
109
110 m5.restoreCheckpoint(root,
111 "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]]))
112
113 if options.standard_switch:
114 exit_event = m5.simulate(10000)
115
116 ## when you change to Timing (or Atomic), you halt the system given
117 ## as argument. When you are finished with the system changes
118 ## (including switchCpus), you must resume the system manually.
119 ## You DON'T need to resume after just switching CPUs if you haven't
120 ## changed anything on the system level.
121
122 m5.changeToTiming(testsys)
123 m5.switchCpus(switch_cpu_list)
124 m5.resume(testsys)
125
126 exit_event = m5.simulate(options.warmup)
127 m5.switchCpus(switch_cpu_list1)
128
129 num_checkpoints = 0
130 exit_cause = ''
131
132 ## Checkpoints being taken via the command line at <when> and at subsequent
133 ## periods of <period>. Checkpoint instructions received from the benchmark running
134 ## are ignored and skipped in favor of command line checkpoint instructions.
135 if options.take_checkpoints:
136 [when, period] = options.take_checkpoints.split(",", 1)
137 when = int(when)
138 period = int(period)
139
140 exit_event = m5.simulate(when)
141 while exit_event.getCause() == "checkpoint":
142 exit_event = m5.simulate(when - m5.curTick())
143
144 if exit_event.getCause() == "simulate() limit reached":
145 m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
146 num_checkpoints += 1
147
148 sim_ticks = when
149 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
150 while num_checkpoints < max_checkpoints:
151 if (sim_ticks + period) > maxtick and maxtick != -1:
152 exit_event = m5.simulate(maxtick - sim_ticks)
153 exit_cause = exit_event.getCause()
154 break
155 else:
156 exit_event = m5.simulate(period)
157 sim_ticks += period
158 while exit_event.getCause() == "checkpoint":
159 exit_event = m5.simulate(sim_ticks - m5.curTick())
160 if exit_event.getCause() == "simulate() limit reached":
161 m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
162 num_checkpoints += 1
163
164 else: #no checkpoints being taken via this script
165 exit_event = m5.simulate(maxtick)
166
167 while exit_event.getCause() == "checkpoint":
168 m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
169 num_checkpoints += 1
170 if num_checkpoints == max_checkpoints:
171 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
172 break
173
174 if maxtick == -1:
175 exit_event = m5.simulate(maxtick)
176 else:
177 exit_event = m5.simulate(maxtick - m5.curTick())
178
179 exit_cause = exit_event.getCause()
180
181 if exit_cause == '':
182 exit_cause = exit_event.getCause()
183 print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
184
|