Simulation.py (8724:7b4d80b26e35) | Simulation.py (8803:f6c5785bc8fd) |
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1# Copyright (c) 2006-2008 The Regents of The University of Michigan 2# Copyright (c) 2010 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 110 unchanged lines hidden (view full) --- 119 if cpu_class: 120 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) 121 for i in xrange(np)] 122 123 for i in xrange(np): 124 if options.fast_forward: 125 testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 126 switch_cpus[i].system = testsys | 1# Copyright (c) 2006-2008 The Regents of The University of Michigan 2# Copyright (c) 2010 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 110 unchanged lines hidden (view full) --- 119 if cpu_class: 120 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) 121 for i in xrange(np)] 122 123 for i in xrange(np): 124 if options.fast_forward: 125 testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 126 switch_cpus[i].system = testsys |
127 if not buildEnv['FULL_SYSTEM']: 128 switch_cpus[i].workload = testsys.cpu[i].workload | 127 switch_cpus[i].workload = testsys.cpu[i].workload |
129 switch_cpus[i].clock = testsys.cpu[0].clock 130 # simulation period 131 if options.maxinsts: 132 switch_cpus[i].max_insts_any_thread = options.maxinsts 133 134 testsys.switch_cpus = switch_cpus 135 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 136 --- 6 unchanged lines hidden (view full) --- 143 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) 144 for i in xrange(np)] 145 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) 146 for i in xrange(np)] 147 148 for i in xrange(np): 149 switch_cpus[i].system = testsys 150 switch_cpus_1[i].system = testsys | 128 switch_cpus[i].clock = testsys.cpu[0].clock 129 # simulation period 130 if options.maxinsts: 131 switch_cpus[i].max_insts_any_thread = options.maxinsts 132 133 testsys.switch_cpus = switch_cpus 134 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 135 --- 6 unchanged lines hidden (view full) --- 142 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) 143 for i in xrange(np)] 144 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) 145 for i in xrange(np)] 146 147 for i in xrange(np): 148 switch_cpus[i].system = testsys 149 switch_cpus_1[i].system = testsys |
151 if not buildEnv['FULL_SYSTEM']: 152 switch_cpus[i].workload = testsys.cpu[i].workload 153 switch_cpus_1[i].workload = testsys.cpu[i].workload | 150 switch_cpus[i].workload = testsys.cpu[i].workload 151 switch_cpus_1[i].workload = testsys.cpu[i].workload |
154 switch_cpus[i].clock = testsys.cpu[0].clock 155 switch_cpus_1[i].clock = testsys.cpu[0].clock 156 157 # if restoring, make atomic cpu simulate only a few instructions 158 if options.checkpoint_restore != None: 159 testsys.cpu[i].max_insts_any_thread = 1 160 # Fast forward to specified location if we are not restoring 161 elif options.fast_forward: --- 225 unchanged lines hidden --- | 152 switch_cpus[i].clock = testsys.cpu[0].clock 153 switch_cpus_1[i].clock = testsys.cpu[0].clock 154 155 # if restoring, make atomic cpu simulate only a few instructions 156 if options.checkpoint_restore != None: 157 testsys.cpu[i].max_insts_any_thread = 1 158 # Fast forward to specified location if we are not restoring 159 elif options.fast_forward: --- 225 unchanged lines hidden --- |