1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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119 if cpu_class:
120 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
121 for i in xrange(np)]
122
123 for i in xrange(np):
124 if options.fast_forward:
125 testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
126 switch_cpus[i].system = testsys
127 switch_cpus[i].workload = testsys.cpu[i].workload
128 switch_cpus[i].clock = testsys.cpu[0].clock
129 # simulation period
130 if options.maxinsts:
131 switch_cpus[i].max_insts_any_thread = options.maxinsts
132
133 testsys.switch_cpus = switch_cpus
134 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
135

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142 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
143 for i in xrange(np)]
144 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
145 for i in xrange(np)]
146
147 for i in xrange(np):
148 switch_cpus[i].system = testsys
149 switch_cpus_1[i].system = testsys
150 switch_cpus[i].workload = testsys.cpu[i].workload
151 switch_cpus_1[i].workload = testsys.cpu[i].workload
152 switch_cpus[i].clock = testsys.cpu[0].clock
153 switch_cpus_1[i].clock = testsys.cpu[0].clock
154
155 # if restoring, make atomic cpu simulate only a few instructions
156 if options.checkpoint_restore != None:
157 testsys.cpu[i].max_insts_any_thread = 1
158 # Fast forward to specified location if we are not restoring
159 elif options.fast_forward:

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