1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
--- 37 unchanged lines hidden (view full) ---
46 else:
47 class TmpClass(AtomicSimpleCPU): pass
48 atomic = True
49
50 CPUClass = None
51 test_mem_mode = 'atomic'
52
53 if not atomic:
54 if options.checkpoint_restore or options.fast_forward:
55 CPUClass = TmpClass
56 class TmpClass(AtomicSimpleCPU): pass
57 else:
58 test_mem_mode = 'timing'
59
60 return (TmpClass, test_mem_mode, CPUClass)
61
62
--- 18 unchanged lines hidden (view full) ---
81 max_checkpoints = options.max_checkpoints
82 switch_cpus = None
83
84 if cpu_class:
85 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
86 for i in xrange(np)]
87
88 for i in xrange(np):
89 if options.fast_forward:
90 testsys.cpu[i].max_insts_any_thread = options.fast_forward
91 switch_cpus[i].system = testsys
92 if not m5.build_env['FULL_SYSTEM']:
93 switch_cpus[i].workload = testsys.cpu[i].workload
94 switch_cpus[i].clock = testsys.cpu[0].clock
95
96 testsys.switch_cpus = switch_cpus
97 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
98
99 if options.standard_switch:
100 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
101 for i in xrange(np)]
102 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
103 for i in xrange(np)]
104
105 for i in xrange(np):
106 switch_cpus[i].system = testsys
107 switch_cpus_1[i].system = testsys
108 if not m5.build_env['FULL_SYSTEM']:
109 switch_cpus[i].workload = testsys.cpu[i].workload
110 switch_cpus_1[i].workload = testsys.cpu[i].workload
111 switch_cpus[i].clock = testsys.cpu[0].clock
112 switch_cpus_1[i].clock = testsys.cpu[0].clock
113
114 # if restoring, make atomic cpu simulate only a few instructions
115 if options.checkpoint_restore:
116 testsys.cpu[i].max_insts_any_thread = 1
117 # Fast forward to specified location if we are not restoring
118 elif options.fast_forward:
119 testsys.cpu[i].max_insts_any_thread = options.fast_forward
120 # Fast forward to a simpoint (warning: time consuming)
121 elif options.simpoint:
122 if testsys.cpu[i].workload[0].simpoint == None:
123 m5.panic('simpoint not found')
124 testsys.cpu[i].max_insts_any_thread = \
125 testsys.cpu[i].workload[0].simpoint
126 # No distance specified, just switch
127 else:
128 testsys.cpu[i].max_insts_any_thread = 1
129
130 # warmup period
131 if options.warmup_insts:
132 switch_cpus[i].max_insts_any_thread = options.warmup_insts
133
134 # simulation period
135 if options.max_inst:
136 switch_cpus_1[i].max_insts_any_thread = options.max_inst
137
138 if not options.caches:
139 # O3 CPU must have a cache to work.
140 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
141 L1Cache(size = '64kB'))
142 switch_cpus_1[i].connectMemPorts(testsys.membus)
143
144 testsys.switch_cpus = switch_cpus
145 testsys.switch_cpus_1 = switch_cpus_1
146 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
147 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
148
149 # set the checkpoint in the cpu before m5.instantiate is called
150 if options.take_checkpoints and \
151 (options.simpoint or options.at_instruction):
152 offset = int(options.take_checkpoints)
153 # Set an instruction break point
154 if options.simpoint:
155 for i in xrange(np):
156 if testsys.cpu[i].workload[0].simpoint == None:
157 m5.panic('no simpoint for testsys.cpu[%d].workload[0]' % i)
158 checkpoint_inst = testsys.cpu[i].workload[0].simpoint + offset
159 testsys.cpu[i].max_insts_any_thread = checkpoint_inst
160 # used for output below
161 options.take_checkpoints = checkpoint_inst
162 else:
163 options.take_checkpoints = offset
164 # Set all test cpus with the right number of instructions
165 # for the upcoming simulation
166 for i in xrange(np):
167 testsys.cpu[i].max_insts_any_thread = offset
168
169 testsys.cpu_switch_list = cpu_switch_list
170
171 m5.instantiate(root)
172
173 if options.checkpoint_restore:
174 from os.path import isdir, exists
175 from os import listdir
176 import re
177
178 if not isdir(cptdir):
179 m5.panic("checkpoint dir %s does not exist!" % cptdir)
180
181 if options.at_instruction:
182 checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % \
183 (options.bench, options.checkpoint_restore))
184 if not exists(checkpoint_dir):
185 m5.panic("Unable to find checkpoint directory %s" % \
186 checkpoint_dir)
187
188 print "Restoring checkpoint ..."
189 m5.restoreCheckpoint(root, checkpoint_dir)
190 print "Done."
191 elif options.simpoint:
192 # assume workload 0 has the simpoint
193 if testsys.cpu[i].workload[0].simpoint == None:
194 m5.panic('Unable to find simpoint')
195
196 options.checkpoint_restore += \
197 testsys.cpu[0].workload[0].simpoint
198
199 checkpoint_dir = joinpath(cptdir, "cpt.%s.%d" % \
200 (options.bench, options.checkpoint_restore))
201 if not exists(checkpoint_dir):
202 m5.panic("Unable to find checkpoint directory %s.%s" % \
203 (options.bench, options.checkpoint_restore))
204
205 print "Restoring checkpoint ..."
206 m5.restoreCheckpoint(root,checkpoint_dir)
207 print "Done."
208 else:
209 dirs = listdir(cptdir)
210 expr = re.compile('cpt\.([0-9]*)')
211 cpts = []
212 for dir in dirs:
213 match = expr.match(dir)
214 if match:
215 cpts.append(match.group(1))
216
217 cpts.sort(lambda a,b: cmp(long(a), long(b)))
218
219 cpt_num = options.checkpoint_restore
220
221 if cpt_num > len(cpts):
222 m5.panic('Checkpoint %d not found' % cpt_num)
223
224 ## Adjust max tick based on our starting tick
225 maxtick = maxtick - int(cpts[cpt_num - 1])
226
227 ## Restore the checkpoint
228 m5.restoreCheckpoint(root,
229 joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]))
230
231 if options.standard_switch or cpu_class:
232 if options.standard_switch:
233 print "Switch at instruction count:%s" % \
234 str(testsys.cpu[0].max_insts_any_thread)
235 exit_event = m5.simulate()
236 elif cpu_class and options.fast_forward:
237 print "Switch at instruction count:%s" % \
238 str(testsys.cpu[0].max_insts_any_thread)
239 exit_event = m5.simulate()
240 else:
241 print "Switch at curTick count:%s" % str(10000)
242 exit_event = m5.simulate(10000)
243 print "Switched CPUS @ cycle = %s" % (m5.curTick())
244
245 # when you change to Timing (or Atomic), you halt the system
246 # given as argument. When you are finished with the system
247 # changes (including switchCpus), you must resume the system
248 # manually. You DON'T need to resume after just switching
249 # CPUs if you haven't changed anything on the system level.
250
251 m5.changeToTiming(testsys)
252 m5.switchCpus(switch_cpu_list)
253 m5.resume(testsys)
254
255 if options.standard_switch:
256 print "Switch at instruction count:%d" % \
257 (testsys.switch_cpus[0].max_insts_any_thread)
258
259 #warmup instruction count may have already been set
260 if options.warmup_insts:
261 exit_event = m5.simulate()
262 else:
263 exit_event = m5.simulate(options.warmup)
264 print "Switching CPUS @ cycle = %s" % (m5.curTick())
265 print "Simulation ends instruction count:%d" % \
266 (testsys.switch_cpus_1[0].max_insts_any_thread)
267 m5.drain(testsys)
268 m5.switchCpus(switch_cpu_list1)
269 m5.resume(testsys)
270
271 num_checkpoints = 0
272 exit_cause = ''
273
274 # Checkpoints being taken via the command line at <when> and at
275 # subsequent periods of <period>. Checkpoint instructions
276 # received from the benchmark running are ignored and skipped in
277 # favor of command line checkpoint instructions.
278 if options.take_checkpoints:
279 when, period = options.take_checkpoints.split(",", 1)
280 when = int(when)
281 period = int(period)
282
283 if options.at_instruction or options.simpoint:
284 checkpoint_inst = when
285
286 # maintain correct offset if we restored from some instruction
287 if options.checkpoint_restore:
288 checkpoint_inst += options.checkpoint_restore
289
290 print "Creating checkpoint at inst:%d" % (checkpoint_inst)
291 exit_event = m5.simulate()
292 print "exit cause = %s" % (exit_event.getCause())
293
294 # skip checkpoint instructions should they exist
295 while exit_event.getCause() == "checkpoint":
296 exit_event = m5.simulate()
297
298 if exit_event.getCause() == \
299 "a thread reached the max instruction count":
300 m5.checkpoint(root, joinpath(cptdir, "cpt.%s.%d" % \
301 (options.bench, checkpoint_inst)))
302 print "Checkpoint written."
303 num_checkpoints += 1
304
305 if exit_event.getCause() == "user interrupt received":
306 exit_cause = exit_event.getCause();
307 else:
308 exit_event = m5.simulate(when)
309 while exit_event.getCause() == "checkpoint":
310 exit_event = m5.simulate(when - m5.curTick())
311
312 if exit_event.getCause() == "simulate() limit reached":
313 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
314 num_checkpoints += 1
315
316 sim_ticks = when
317 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
318 while num_checkpoints < max_checkpoints and \
319 exit_event.getCause() == "simulate() limit reached":
320 if (sim_ticks + period) > maxtick:
321 exit_event = m5.simulate(maxtick - sim_ticks)
322 exit_cause = exit_event.getCause()
323 break
324 else:
325 exit_event = m5.simulate(period)
326 sim_ticks += period
327 while exit_event.getCause() == "checkpoint":
328 exit_event = m5.simulate(sim_ticks - m5.curTick())
329 if exit_event.getCause() == "simulate() limit reached":
330 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
331 num_checkpoints += 1
332
333 if exit_event.getCause() != "simulate() limit reached":
334 exit_cause = exit_event.getCause();
335
336 else: # no checkpoints being taken via this script
337 if options.fast_forward:
338 m5.stats.reset()
339 print "**** REAL SIMULATION ****"
340 exit_event = m5.simulate(maxtick)
341
342 while exit_event.getCause() == "checkpoint":
343 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
344 num_checkpoints += 1
345 if num_checkpoints == max_checkpoints:
346 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
347 break
348
349 exit_event = m5.simulate(maxtick - m5.curTick())
350 exit_cause = exit_event.getCause()
351
352 if exit_cause == '':
353 exit_cause = exit_event.getCause()
354 print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause)
355
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
--- 37 unchanged lines hidden (view full) ---
46 else:
47 class TmpClass(AtomicSimpleCPU): pass
48 atomic = True
49
50 CPUClass = None
51 test_mem_mode = 'atomic'
52
53 if not atomic:
54 if options.checkpoint_restore or options.fast_forward:
55 CPUClass = TmpClass
56 class TmpClass(AtomicSimpleCPU): pass
57 else:
58 test_mem_mode = 'timing'
59
60 return (TmpClass, test_mem_mode, CPUClass)
61
62
--- 18 unchanged lines hidden (view full) ---
81 max_checkpoints = options.max_checkpoints
82 switch_cpus = None
83
84 if cpu_class:
85 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
86 for i in xrange(np)]
87
88 for i in xrange(np):
89 if options.fast_forward:
90 testsys.cpu[i].max_insts_any_thread = options.fast_forward
91 switch_cpus[i].system = testsys
92 if not m5.build_env['FULL_SYSTEM']:
93 switch_cpus[i].workload = testsys.cpu[i].workload
94 switch_cpus[i].clock = testsys.cpu[0].clock
95
96 testsys.switch_cpus = switch_cpus
97 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
98
99 if options.standard_switch:
100 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
101 for i in xrange(np)]
102 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
103 for i in xrange(np)]
104
105 for i in xrange(np):
106 switch_cpus[i].system = testsys
107 switch_cpus_1[i].system = testsys
108 if not m5.build_env['FULL_SYSTEM']:
109 switch_cpus[i].workload = testsys.cpu[i].workload
110 switch_cpus_1[i].workload = testsys.cpu[i].workload
111 switch_cpus[i].clock = testsys.cpu[0].clock
112 switch_cpus_1[i].clock = testsys.cpu[0].clock
113
114 # if restoring, make atomic cpu simulate only a few instructions
115 if options.checkpoint_restore:
116 testsys.cpu[i].max_insts_any_thread = 1
117 # Fast forward to specified location if we are not restoring
118 elif options.fast_forward:
119 testsys.cpu[i].max_insts_any_thread = options.fast_forward
120 # Fast forward to a simpoint (warning: time consuming)
121 elif options.simpoint:
122 if testsys.cpu[i].workload[0].simpoint == None:
123 m5.panic('simpoint not found')
124 testsys.cpu[i].max_insts_any_thread = \
125 testsys.cpu[i].workload[0].simpoint
126 # No distance specified, just switch
127 else:
128 testsys.cpu[i].max_insts_any_thread = 1
129
130 # warmup period
131 if options.warmup_insts:
132 switch_cpus[i].max_insts_any_thread = options.warmup_insts
133
134 # simulation period
135 if options.max_inst:
136 switch_cpus_1[i].max_insts_any_thread = options.max_inst
137
138 if not options.caches:
139 # O3 CPU must have a cache to work.
140 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
141 L1Cache(size = '64kB'))
142 switch_cpus_1[i].connectMemPorts(testsys.membus)
143
144 testsys.switch_cpus = switch_cpus
145 testsys.switch_cpus_1 = switch_cpus_1
146 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
147 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
148
149 # set the checkpoint in the cpu before m5.instantiate is called
150 if options.take_checkpoints and \
151 (options.simpoint or options.at_instruction):
152 offset = int(options.take_checkpoints)
153 # Set an instruction break point
154 if options.simpoint:
155 for i in xrange(np):
156 if testsys.cpu[i].workload[0].simpoint == None:
157 m5.panic('no simpoint for testsys.cpu[%d].workload[0]' % i)
158 checkpoint_inst = testsys.cpu[i].workload[0].simpoint + offset
159 testsys.cpu[i].max_insts_any_thread = checkpoint_inst
160 # used for output below
161 options.take_checkpoints = checkpoint_inst
162 else:
163 options.take_checkpoints = offset
164 # Set all test cpus with the right number of instructions
165 # for the upcoming simulation
166 for i in xrange(np):
167 testsys.cpu[i].max_insts_any_thread = offset
168
169 testsys.cpu_switch_list = cpu_switch_list
170
171 m5.instantiate(root)
172
173 if options.checkpoint_restore:
174 from os.path import isdir, exists
175 from os import listdir
176 import re
177
178 if not isdir(cptdir):
179 m5.panic("checkpoint dir %s does not exist!" % cptdir)
180
181 if options.at_instruction:
182 checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % \
183 (options.bench, options.checkpoint_restore))
184 if not exists(checkpoint_dir):
185 m5.panic("Unable to find checkpoint directory %s" % \
186 checkpoint_dir)
187
188 print "Restoring checkpoint ..."
189 m5.restoreCheckpoint(root, checkpoint_dir)
190 print "Done."
191 elif options.simpoint:
192 # assume workload 0 has the simpoint
193 if testsys.cpu[i].workload[0].simpoint == None:
194 m5.panic('Unable to find simpoint')
195
196 options.checkpoint_restore += \
197 testsys.cpu[0].workload[0].simpoint
198
199 checkpoint_dir = joinpath(cptdir, "cpt.%s.%d" % \
200 (options.bench, options.checkpoint_restore))
201 if not exists(checkpoint_dir):
202 m5.panic("Unable to find checkpoint directory %s.%s" % \
203 (options.bench, options.checkpoint_restore))
204
205 print "Restoring checkpoint ..."
206 m5.restoreCheckpoint(root,checkpoint_dir)
207 print "Done."
208 else:
209 dirs = listdir(cptdir)
210 expr = re.compile('cpt\.([0-9]*)')
211 cpts = []
212 for dir in dirs:
213 match = expr.match(dir)
214 if match:
215 cpts.append(match.group(1))
216
217 cpts.sort(lambda a,b: cmp(long(a), long(b)))
218
219 cpt_num = options.checkpoint_restore
220
221 if cpt_num > len(cpts):
222 m5.panic('Checkpoint %d not found' % cpt_num)
223
224 ## Adjust max tick based on our starting tick
225 maxtick = maxtick - int(cpts[cpt_num - 1])
226
227 ## Restore the checkpoint
228 m5.restoreCheckpoint(root,
229 joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]))
230
231 if options.standard_switch or cpu_class:
232 if options.standard_switch:
233 print "Switch at instruction count:%s" % \
234 str(testsys.cpu[0].max_insts_any_thread)
235 exit_event = m5.simulate()
236 elif cpu_class and options.fast_forward:
237 print "Switch at instruction count:%s" % \
238 str(testsys.cpu[0].max_insts_any_thread)
239 exit_event = m5.simulate()
240 else:
241 print "Switch at curTick count:%s" % str(10000)
242 exit_event = m5.simulate(10000)
243 print "Switched CPUS @ cycle = %s" % (m5.curTick())
244
245 # when you change to Timing (or Atomic), you halt the system
246 # given as argument. When you are finished with the system
247 # changes (including switchCpus), you must resume the system
248 # manually. You DON'T need to resume after just switching
249 # CPUs if you haven't changed anything on the system level.
250
251 m5.changeToTiming(testsys)
252 m5.switchCpus(switch_cpu_list)
253 m5.resume(testsys)
254
255 if options.standard_switch:
256 print "Switch at instruction count:%d" % \
257 (testsys.switch_cpus[0].max_insts_any_thread)
258
259 #warmup instruction count may have already been set
260 if options.warmup_insts:
261 exit_event = m5.simulate()
262 else:
263 exit_event = m5.simulate(options.warmup)
264 print "Switching CPUS @ cycle = %s" % (m5.curTick())
265 print "Simulation ends instruction count:%d" % \
266 (testsys.switch_cpus_1[0].max_insts_any_thread)
267 m5.drain(testsys)
268 m5.switchCpus(switch_cpu_list1)
269 m5.resume(testsys)
270
271 num_checkpoints = 0
272 exit_cause = ''
273
274 # Checkpoints being taken via the command line at <when> and at
275 # subsequent periods of <period>. Checkpoint instructions
276 # received from the benchmark running are ignored and skipped in
277 # favor of command line checkpoint instructions.
278 if options.take_checkpoints:
279 when, period = options.take_checkpoints.split(",", 1)
280 when = int(when)
281 period = int(period)
282
283 if options.at_instruction or options.simpoint:
284 checkpoint_inst = when
285
286 # maintain correct offset if we restored from some instruction
287 if options.checkpoint_restore:
288 checkpoint_inst += options.checkpoint_restore
289
290 print "Creating checkpoint at inst:%d" % (checkpoint_inst)
291 exit_event = m5.simulate()
292 print "exit cause = %s" % (exit_event.getCause())
293
294 # skip checkpoint instructions should they exist
295 while exit_event.getCause() == "checkpoint":
296 exit_event = m5.simulate()
297
298 if exit_event.getCause() == \
299 "a thread reached the max instruction count":
300 m5.checkpoint(root, joinpath(cptdir, "cpt.%s.%d" % \
301 (options.bench, checkpoint_inst)))
302 print "Checkpoint written."
303 num_checkpoints += 1
304
305 if exit_event.getCause() == "user interrupt received":
306 exit_cause = exit_event.getCause();
307 else:
308 exit_event = m5.simulate(when)
309 while exit_event.getCause() == "checkpoint":
310 exit_event = m5.simulate(when - m5.curTick())
311
312 if exit_event.getCause() == "simulate() limit reached":
313 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
314 num_checkpoints += 1
315
316 sim_ticks = when
317 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
318 while num_checkpoints < max_checkpoints and \
319 exit_event.getCause() == "simulate() limit reached":
320 if (sim_ticks + period) > maxtick:
321 exit_event = m5.simulate(maxtick - sim_ticks)
322 exit_cause = exit_event.getCause()
323 break
324 else:
325 exit_event = m5.simulate(period)
326 sim_ticks += period
327 while exit_event.getCause() == "checkpoint":
328 exit_event = m5.simulate(sim_ticks - m5.curTick())
329 if exit_event.getCause() == "simulate() limit reached":
330 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
331 num_checkpoints += 1
332
333 if exit_event.getCause() != "simulate() limit reached":
334 exit_cause = exit_event.getCause();
335
336 else: # no checkpoints being taken via this script
337 if options.fast_forward:
338 m5.stats.reset()
339 print "**** REAL SIMULATION ****"
340 exit_event = m5.simulate(maxtick)
341
342 while exit_event.getCause() == "checkpoint":
343 m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
344 num_checkpoints += 1
345 if num_checkpoints == max_checkpoints:
346 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
347 break
348
349 exit_event = m5.simulate(maxtick - m5.curTick())
350 exit_cause = exit_event.getCause()
351
352 if exit_cause == '':
353 exit_cause = exit_event.getCause()
354 print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause)
355