1# Copyright (c) 2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 95 unchanged lines hidden (view full) ---

104 parser.add_option("--l2_assoc", type="int", default=8)
105 parser.add_option("--l3_assoc", type="int", default=16)
106 parser.add_option("--cacheline_size", type="int", default=64)
107
108 # Enable Ruby
109 parser.add_option("--ruby", action="store_true")
110
111 # Run duration options
112 parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
113 metavar="T", help="Stop after T ticks")
114 parser.add_option("--maxtime", type="float")
115 parser.add_option("-I", "--maxinsts", action="store", type="int",
116 default=None, help="""Total number of instructions to
117 simulate (default: run forever)""")
118 parser.add_option("--work-item-id", action="store", type="int",
119 help="the specific work id for exit & checkpointing")
120 parser.add_option("--work-begin-cpu-id-exit", action="store", type="int",
121 help="exit when work starts on the specified cpu")
122 parser.add_option("--work-end-exit-count", action="store", type="int",

--- 115 unchanged lines hidden ---